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| DATA SHEET PD784907, 784908 16-BIT SINGLE-CHIP MICROCONTROLLER MOS INTEGRATED CIRCUIT The PD784907 and PD784908 are products of the PD784908 Subseries in the 78K/IV Series. These products contain various peripheral hardware such as IEBusTM controller, ROM, RAM, I/O ports, 8-bit resolution A/D, timers, serial interface, and interrupt functions, as well as a high-speed, high-performance CPU. In addition, the PD78P4908 (one-time PROM product), which is used to evaluate the functions of mask ROM versions, and development tools are also available. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. PD784908 Subseries User's Manual Hardware : U11787E 78K/IV Series User's Manual Instruction : U10905E FEATURES * 78K/IV Series * Minimum instruction execution time: 320 ns (at 6.29 MHz) 160 ns (at 12.58 MHz) * Watchdog timer: 1 channel * Clock output function Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 * Number of I/O ports: 80 * Timer/counters: 16-bit timer/counter x 3 units 16-bit timer x 1 unit * Serial interface: 4 channels UART/IOE (3-wire serial I/O): 2 channels CSI (3-wire serial I/O): 2 channels * A/D converter: 8-bit resolution x 8 channels * On-chip IEBus controller * Watch timer * Low-power consumption * Supply voltage: VDD = 4.0 to 5.5 V (Main clock: fXX = 12.58 MHz, internal system clock = fXX, fCYK = 79 ns) VDD = 3.5 to 5.5 V (Other than above, fCYK = 159 ns) * PWM outputs: 2 * Standby function HALT/STOP/IDLE mode * Clock frequency division function APPLICATIONS Car audios, etc. This document describes the PD784908 unless otherwise specified. The information in this document is subject to change without notice. Document No. U11680EJ2V0DS00 (2nd edition) Date Published February 1999 N CP(K) Printed in Japan The mark shows major revised points. (c) 1996 PD784907, 784908 ORDERING INFORMATION Part number Package 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) Internal ROM (bytes) Internal RAM (bytes) 3,584 4,352 PD784907GF-xxx-3BA PD784908GF-xxx-3BA 96 K 128 K Remark xxx indicates ROM code suffix. 2 Data Sheet U11680EJ2V0DS00 PD784907, 784908 78K/IV SERIES PRODUCT LINEUP : Under mass production : Under development I2C bus supported Multi-master I2C bus supported PD784038Y Standard models PD784225Y PD784225 80 pins, ROM correction added Multi-master I2C bus supported PD784038 Enhanced internal memory capacity, pin compatible with the PD784026 Multi-master I2C bus supported PD784026 Enhanced A/D, 16-bit timer, and power management PD784216Y PD784216 100 pins, enhanced I/O and internal memory capacity PD784218Y PD784218 Enhanced internal memory capacity, ROM correction added PD784054 PD784046 ASSP models On-chip 10-bit A/D PD784955 For DC inverter control PD784938 PD784908 On-chip IEBus controller Enhanced functions of the PD784908, enhanced internal memory capacity, ROM correction added Multi-master I2C bus supported PD784928Y PD784928 PD784915 For software servo control, on-chip analog circuit for VCR, enhanced timer Enhanced functions of the PD784915 Data Sheet U11680EJ2V0DS00 3 PD784907, 784908 FUNCTIONS Part Number Item Number of basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space I/O ports Total Input Input/output Additional function pins Note LED direct drive outputs Transistor direct drive N-ch open drain Real-time output ports IEBus controller Timer/counter ROM RAM 113 8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping) 320 ns/636 ns/1.27 s/2.54 s (at 6.29 MHz) 160 ns/320 ns/636 ns/1.27 s (at 12.58 MHz) 96 K 3,584 bytes 128 K 4,352 bytes PD784907 PD784908 1 Mbyte with program and data spaces combined 80 8 72 24 8 4 4 bits x 2, or 8 bits x 1 Incorporated (simplified) Timer/counter 0: (16 bits) Timer register x 1 Capture register x 1 Compare register x 2 Timer register x 1 Capture register x 1 Capture/compare register x 1 Compare register x 1 Timer register x 1 Capture register x 1 Capture/compare register x 1 Compare register x 1 Timer register x 1 Compare register x 1 Pulse output capability * Toggle output * PWM/PPG output * One-shot pulse output Real-time output port Timer/counter 1: (16 bits) Timer/counter 2: (16 bits) Pulse output capability * Toggle output * PWM/PPG output Timer 3: (16 bits) Watch timer Interrupt requests are generated at 0.5-second intervals. (A watch clock oscillator is incorporated.) Either the main clock (6.29 MHz/12.58 MHz) or watch clock (32.7 kHz) can be selected as the input clock. Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 (can be used as a 1-bit output port) 12-bit resolution x 2 channels UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator) CSI (3-wire serial I/O): 2 channels 8-bit resolution x 8 channels Clock output PWM outputs Serial interface A/D converter Note Additional function pins are included in the I/O pins. 4 Data Sheet U11680EJ2V0DS00 PD784907, 784908 Part Number Item Watchdog timer Standby Interrupt Hardware source Software source Non-maskable Maskable 1 channel PD784907 PD784908 HALT/STOP/IDLE modes 27 (20 internal, 7 external (sampling clock variable input: 1)) BRK or BRKCS instruction, operand error 1 internal, 1 external 19 internal, 6 external 4-level programmable priority 3 operation statuses: vectored interrupt, macro service, context switching Power supply voltage Package VDD = 4.0 to 5.5 V (Main clock: fXX = 12.58 MHz, internal system clock = fXX, fCYK = 79 ns) VDD = 3.5 to 5.5 V (other than above, fCYK = 159 ns) 100-pin plastic QFP (14 x 20 mm) Data Sheet U11680EJ2V0DS00 5 PD784907, 784908 CONTENTS 1. 2. 3. 4. 5. 6. DIFFERENCES BETWEEN PD784908 SUBSERIES PRODUCTS ....................................... MAJOR DIFFERENCES BETWEEN PD784908 AND PD78098 SUBSERIES .................. PIN CONFIGURATION (TOP VIEW) ......................................................................................... SYSTEM CONFIGURATION EXAMPLE (AUTOMOTIVE CAR AUDIO (TUNER DECK)) ..... BLOCK DIAGRAM ..................................................................................................................... PIN FUNCTION ........................................................................................................................... 6.1 6.2 6.3 Port Pins ............................................................................................................................................ Non-Port Pins ................................................................................................................................... Pin I/O Circuits and Recommended Connections of Unused Pins .......................................... 8 9 10 12 13 14 14 16 18 7. CPU ARCHITECTURE ............................................................................................................... 7.1 7.2 Memory Space .................................................................................................................................. CPU Registers .................................................................................................................................. 7.2.1 7.2.2 7.2.3 General-purpose registers ................................................................................................ Control registers ................................................................................................................ Special function registers (SFRs) .................................................................................... 22 22 25 25 26 27 8. PERIPHERAL HARDWARE FUNCTIONS ................................................................................ 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 Ports ................................................................................................................................................... Clock Generator ............................................................................................................................... Real-Time Output Port ..................................................................................................................... Timers/Counters ............................................................................................................................... Watch Timer ...................................................................................................................................... PWM Output (PWM0, PWM1) .......................................................................................................... A/D Converter ................................................................................................................................... Serial Interface ................................................................................................................................. 8.8.1 8.8.2 8.9 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ....................................... Clocked serial interface (CSI) ........................................................................................... 33 33 35 38 39 41 42 43 44 45 47 48 49 49 50 Clock Output Function .................................................................................................................... 8.10 Edge Detection Function ................................................................................................................ 8.11 Watchdog Timer ............................................................................................................................... 8.12 Simplified IEBus Controller ............................................................................................................ 9. INTERRUPT FUNCTION ............................................................................................................ 9.1 9.2 9.3 9.4 9.5 Interrupt Source ............................................................................................................................... Vectored Interrupt ............................................................................................................................ Context Switching ............................................................................................................................ Macro Service ................................................................................................................................... Examples of Macro Service Applications .................................................................................... 53 53 55 56 56 57 6 Data Sheet U11680EJ2V0DS00 PD784907, 784908 10. LOCAL BUS INTERFACE ......................................................................................................... 10.1 Memory Expansion .......................................................................................................................... 10.2 Memory Space .................................................................................................................................. 10.3 Programmable Wait ......................................................................................................................... 10.4 Pseudo-Static RAM Refresh Function .......................................................................................... 10.5 Bus Hold Function ........................................................................................................................... 59 59 60 61 61 61 11. STANDBY FUNCTION ............................................................................................................... 12. RESET FUNCTION ..................................................................................................................... 13. REGULATOR .............................................................................................................................. 14. INSTRUCTION SET .................................................................................................................... 15. ELECTRICAL SPECIFICATIONS .............................................................................................. 16. PACKAGE DRAWING ................................................................................................................ 17. RECOMMENDED SOLDERING CONDITIONS ........................................................................ APPENDIX A DEVELOPMENT TOOLS .......................................................................................... APPENDIX B RELATED DOCUMENTS ......................................................................................... 62 63 64 65 70 89 90 91 94 Data Sheet U11680EJ2V0DS00 7 PD784907, 784908 1. DIFFERENCES BETWEEN PD784908 SUBSERIES PRODUCTS The only difference between the PD784907 and PD784908 is their internal memory capacities. The PD78P4908 is produced by replacing the mask ROM in the PD784907 or PD784908 with 128-Kbyte onetime PROM. Table 1-1 shows the differences between these products. Table 1-1. Differences between the PD784908 Subseries Products Part Number Item Internal ROM Internal RAM Regulator Power supply voltage 96 K (mask ROM) 3,584 bytes 128 K (mask ROM) 4,352 bytes Provided VDD = 4.0 to 5.5 V (Main clock: fXX = 12.58 MHz, internal system clock = fXX, fCYK = 79 ns) VDD = 3.5 to 5.5 V (other than above, fCYK = 159 ns) None VDD = 4.5 to 5.5 V (Main clock: fXX = 12.58 MHz, internal system clock = fXX, fCYK = 79 ns) VDD = 4.0 to 5.5 V (other than above, fCYK = 159 ns) 128 K (one-time PROM) PD784907 PD784908 PD78P4908 Electrical specifications Refer to the data sheet of each product. 8 Data Sheet U11680EJ2V0DS00 PD784907, 784908 2. MAJOR DIFFERENCES BETWEEN PD784908 AND PD78098 SUBSERIES Series Name Item Number of basic instructions (mnemonics) Minimum instruction execution time Timer/counter 113 320/160 ns (at 6.29/12.58 MHz operation) 16-bit timer/counter x 1 8/16-bit timer/counter x 2 8/16-bit timer x 1 Watch timer Single clock Watch clock for clock operation Watchdog timer Serial interface Provided UART/IOE (3-wire serial I/O): 2 channels CSI (3-wire serial I/O): 2 channels 2 8-bit resolution x 8 channels None Hardware source Internal External External extended function IEBus controller Power supply voltage 27 20 7 Provided (up to 1 Mbyte) Incorporated (simplified) * Mask ROM version VDD = 4.0 to 5.5 V (Main clock: fXX = 12.58 MHz, internal system clock = fXX, fCYK = 79 ns) VDD = 3.5 to 5.5 V (other than above, fCYK = 159 ns) * PROM version VDD = 4.5 to 5.5 V (Main clock: fXX = 12.58 MHz, internal system clock = fXX, fCYK = 79 ns) VDD = 4.0 to 5.5 V (other than above, fCYK = 159 ns) 100-pin plastic QFP (14 x 20 mm) 23 (two test flags) 14 7 None Incorporated (complete hardware) VDD = 2.7 to 6.0 V UART (3-wire serial I/O): 1 channel CSI/SBI (3-wire serial I/O): 1 channel CSI (3-wire serial I/O): 1 channel None Dual clock 63 480 ns (at 6.29 MHz operation) 16-bit timer/counter x 1 8/16-bit timer/counter x 2 Watch timer PD784908 Subseries PD78098 Subseries PWM output A/D converter D/A converter Interrupt Package 80-pin plastic QFP (14 x 14 mm) 80-pin plastic WQFN (14 x 14 mm): PD78P098A only Data Sheet U11680EJ2V0DS00 9 PD784907, 784908 3. PIN CONFIGURATION (TOP VIEW) * 100-pin plastic QFP (14 x 20 mm) PD784907GF-xxx-3BA PD784908GF-xxx-3BA P30/RxD/SI1 P27/SI0 P26/INTP5 P25/INTP4/ASCK/SCK1 P24/INTP3 P23/INTP2/CI P34/TO0 P33/SO0 P32/SCK0 P31/TxD/SO1 P22/INTP1 P21/INTP0 P20/NMI TX RX AVSS P36/TO2 P37/TO3 P100 P101 P102 P103 P104 P105/SCK3 P106/SI3 P107/SO3 RESET XT2 XT1 VSS X2 X1 REGOFF Note 2 REGC Note 3 VDD P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/HLDAK P66/WAIT/HLDRQ P65/WR 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 74 7 73 8 9 72 71 10 70 11 12 69 13 68 14 67 15 66 65 16 17 64 18 63 62 19 20 61 60 21 59 22 58 23 57 24 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AVREF1 AVDD P77/ANI7 P35/TO1 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 TEST Note 1 PWM1 PWM0 P17 P16 P15 P14/TxD2/SO2 P13/RxD2/SI2 P12/ASCK2/SCK2 P11 P10 ASTB/CLKOUT P90 P91 P92 P93 P94 P95 P96 P97 P40/AD0 P41/AD1 P42/AD2 P64/RD P63/A19 P62/A18 P61/A17 P60/A16 P57/A15 P56/A14 P55/A13 P54/A12 VSS VDD P53/A11 Notes 1. Connect the TEST pin directly to VSS. 2. Connect the REGOFF pin directly to VSS (select regulator operation). 3. Connect the REGC pin to VSS via a capacitor of the order of 1 F. 10 Data Sheet U11680EJ2V0DS00 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 PD784907, 784908 A8 to A19: AD0 to AD7: ANI0 to ANI7: ASCK, ASCK2: ASTB: AVDD: AVREF1: AVSS: CI: CLKOUT: HLDAK: HLDRQ: NMI: P00 to P07: P10 to P17: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P67: P70 to P77: P90 to P97: P100 to P107: Address bus Address/data bus Analog input Asynchronous serial clock Address strobe Analog power supply Reference voltage Analog ground Clock input Clock output Hold acknowledge Hold request Non-maskable interrupt Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 9 Port 10 PWM0, PWM1: RD: REFRQ: REGC: REGOFF: RESET: RX: RXD, RXD2: SI0 to SI3: SO0 to SO3: TEST: TO0 to TO3: TX: TXD, TXD2: VDD: VSS: WAIT: WR: X1, X2: XT1, XT2: Pulse width modulation output Read strobe Refresh request Regulator capacitance Regulator off Reset IEBus receive data Receive data Serial input Serial output Test Timer output IEBus transmit data Transmit data Power supply Ground Wait Write strobe Crystal (main system clock) Crystal (watch) SCK0 to SCK3: Serial clock INTP0 to INTP5: Interrupt from peripherals Data Sheet U11680EJ2V0DS00 11 PD784907, 784908 4. SYSTEM CONFIGURATION EXAMPLE (AUTOMOTIVE CAR AUDIO (TUNER DECK)) Front panel Remote-controll signal reception circuit PD784908 IEBus Interrupt input General-purpose port PC2800A, etc. FIPTM Key matrix Cassette deck unit 3-wire serial I/O FIP controller/driver CD unit Tuner pack CD changer, one CD, etc. PD16312, etc. LED display Audio control circuit Electronic volume EEPROMTM SIO with automatic transmission/reception function REGOFF DSP unit REGC 3-wire serial I/O IEBus controller IEBus driver/ receiver TV unit 12 Data Sheet U11680EJ2V0DS00 PD784907, 784908 5. BLOCK DIAGRAM RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 NMI INTP0 to INTP5 INTP3 TO0 TO1 Programmable interrupt controller UART/IOE2 Baud-rate generator UART/IOE1 Baud-rate generator Timer/counter 0 (16 bits) INTP0 Timer/counter 1 (16 bits) Clocked serial interface Timer/counter 2 (16 bits) SCK0 SO0 SI0 78K /IV CPU core ROM SCK3 Clocked serial interface 3 SO3 SI3 Clock output ASTB /CLKOUT AD0 to AD7 A8 to A15 Bus interface A16 to A19 RD WR WAIT/HLDRQ REFRQ/HLDAK P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P90 to P97 P100 to P107 INTP1 INTP2/CI TO2 TO3 Timer 3 (16 bits) P00 to P03 Real-time output port P04 to P07 PWM0 PWM PWM1 ANI0 to ANI7 AVDD AVREF1 AVSS INTP5 Port 3 TX IEBus controller RX RESET TEST X1 X2 REGC REGOFF VDD VSS XT1 Watch timer XT2 Port 10 Port 4 Port 5 System control (regulator) Port 6 Port 7 Port 9 A/D converter Port 2 RAM Port 0 Port 1 Watchdog timer Remark The internal ROM and RAM capacities differ depending on the product. Data Sheet U11680EJ2V0DS00 13 PD784907, 784908 6. PIN FUNCTIONS 6.1 Port Pins (1/2) I/O I/O Alternate Function -- Function Port 0 (P0): * 8-bit I/O port. * Can be used as a real-time output port (4 bits x 2). * Input and output can be specified by 1-bit units. * The use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. * Can drive transistors. Port 1 (P1): * 8-bit I/O port. * Input and output can be specified in 1-bit units. * The use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. * Can drive LEDs. Pin Name P00 to P07 P10 P11 P12 P13 P14 P15 to P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 to P37 P40 to P47 I/O -- -- ASCK2/SCK2 RxD2/SI2 TxD2/SO2 -- Input NMI INTP0 INTP1 INTP2/CI INTP3 INTP4/ASCK/SCK1 INTP5 SI0 Port 2 (P2): * 8-bit input port. * P20 does not function as a general-purpose port (non-maskable interrupt). However, the input level can be checked by an interrupt service routine. * The use of on-chip pull-up resistors can be specified by software for pins P22 to P27 (in 6-bit units). * The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by a CSIM1 specification. I/O RxD/SI1 TxD/SO1 SCK0 SO0 TO0 to TO3 Port 3 (P3): * 8-bit I/O port. * Input and output can be specified in 1-bit units. * The use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. * The use of the N-ch open drain can be specified for pins P32 and P33. Port 4 (P4): * 8-bit I/O port. * Input and output can be specified in 1-bit units. * The use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. * Can drive LEDs. Port 5 (P5): * 8-bit I/O port. * Input and output can be specified in 1-bit units. * The use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. * Can drive LEDs. I/O AD0 to AD7 P50 to P57 I/O A8 to A15 14 Data Sheet U11680EJ2V0DS00 PD784907, 784908 6.1 Port Pins (2/2) I/O I/O Alternate Function A16 to A19 RD WR WAIT/HLDRQ REFRQ/HLDAK I/O ANI0 to ANI7 Port 7 (P7): * 8-bit I/O port. * Input and output can be specified in 1-bit units. Port 9 (P9): * 8-bit I/O port. * Input and output can be specified in 1-bit units. * The use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. Port 10 (P10): * 8-bit I/O port. * Input and output can be specified in 1-bit units. * The use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. * The use of the N-ch open drain can be specified for pins P105 and P107. Function Port 6 (P6): * 8-bit I/O port. * Input and output can be specified in 1-bit units. * The use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. Pin Name P60 to P63 P64 P65 P66 P67 P70 to P77 P90 to P97 I/O -- P100 to P104 P105 P106 P107 I/O SCK3 SI3 SO3 -- Data Sheet U11680EJ2V0DS00 15 PD784907, 784908 6.2 Non-Port Pins (1/2) I/O Output Input Input Alternate Function P34 to P37 P23/INTP2 P30/SI1 P13/SI2 Output P31/SO1 P14/SO2 Input P25/INTP4/SCK1 P12/SCK2 Input P27 P30/RxD P13/RxD2 P106 Output P33 P31/TxD P14/TxD2 P107 I/O P32 P25/INTP4/ASCK P12/ASCK2 P105 Input P20 P21 P22 P23/CI P24 P25/ASCK/SCK1 P26 I/O Output Output Output Output Input Output Input Output Output P40 to P47 P50 to P57 P60 to P63 P64 P65 P66/HLDRQ P67/HLDAK P66/WAIT P67/REFRQ CLKOUT Timer output Input of a count clock for timer/counter 2 Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data input (3-wire serial I/O 0) Serial data input (3-wire serial I/O 1) Serial data input (3-wire serial I/O 2) Serial data input (3-wire serial I/O 3) Serial data output (3-wire serial I/O 0) Serial data output (3-wire serial I/O 1) Serial data output (3-wire serial I/O 2) Serial data output (3-wire serial I/O 3) Serial clock I/O (3-wire serial I/O 0) Serial clock I/O (3-wire serial I/O 1) Serial clock I/O (3-wire serial I/O 2) Serial clock I/O (3-wire serial I/O 3) External interrupt request -- * Input of a count clock for timer/counter 1 * Capture/trigger signal for CR11 or CR12 INTP1 INTP2 INTP3 INTP4 INTP5 AD0 to AD7 A8 to A15 A16 to A19 RD WR WAIT REFRQ HLDRQ HLDAK ASTB * Input of a count clock for timer/counter 2 * Capture/trigger signal for CR22 * Input of a count clock for timer/counter 2 * Capture/trigger signal for CR21 * Input of a count clock for timer/counter 0 * Capture/trigger signal for CR02 -- Input of a conversion start trigger for A/D converter Time multiplexing address/data bus (for connecting external memory) High-order address bus (for connecting external memory) High-order address bus during address expansion (for connecting external memory) Strobe signal output for reading the contents of external memory Strobe signal output for writing on external memory Wait insertion Refresh pulse output to external pseudo static memory Input of bus hold request Output of bus hold response Latch timing output of time multiplexing address (A0 to A7) (for connecting external memory) Function Pin Name TO0 to TO3 CI RxD RxD2 TxD TxD2 ASCK ASCK2 SI0 SI1 SI2 SI3 SO0 SO1 SO2 SO3 SCK0 SCK1 SCK2 SCK3 NMI INTP0 16 Data Sheet U11680EJ2V0DS00 PD784907, 784908 6.2 Non-Port Pins (2/2) I/O Output Output Output Input Output -- -- Input Input -- Input -- Input -- -- -- P70 to P77 -- Analog voltage input for A/D converter To apply the reference voltage for A/D converter Positive power supply for A/D converter GND for A/D converter Positive power supply GND Input Connect directly to VSS. (This pin is for IC test.) Alternate Function ASTB -- -- -- -- -- -- -- -- Clock output PWM output 0 PWM output 1 Data input (IEBus) Data output (IEBus) Capacitance connection for stabilizing the regulator output/power supply when the regulator is stopped. Connect to VSS via a capacitor of order of 1F. Signal for specifying regulator operation Chip reset Crystal input for system clock oscillation (A clock pulse can also be input to the X1 pin.) Watch clock connection Function Pin Name CLKOUT PWM0 PWM1 RX TX REGC REGOFF RESET X1 X2 XT1 XT2 ANI0 to ANI7 AVREF1 AVDD AVSS VDD VSS TEST Data Sheet U11680EJ2V0DS00 17 PD784907, 784908 6.3 Pin I/O Circuits and Recommended Connections of Unused Pins The input/output circuit type of each pin and recommended connections of unused pins are shown in Table 6-1. For each type of input/output circuit, refer to Figure 6-1. Table 6-1. Types of Pin I/O Circuits and Recommended Connections of Unused Pins (1/2) Pin Name P00 to P07 P10, P11 P12/ASCK2/SCK2 P13/RxD2/SI2 P14/TxD2/SO2 P15 to P17 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 P26/INTP5 P27/SI0 P30/RxD/SI1 P31/TxD/SO1 P32/SCK0 P33/SO0 P34/TO0 to P37/TO3 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0 to P77/ANI7 P90 to P97 P100 to P104 P105/SCK3 P106/SI3 P107/SO3 ASTB/CLKOUT 10-A 8-A 10-A 4 Output Leave open 20 5-A I/O Input: Connect to VDD or VSS Output: Leave open 5-A 10-A 5-A I/O Input: Connect to VDD Output: Leave open 8-A 2-A I/O Input Input: Connect to VDD Output: Leave open Connect to VDD 2-A Connect to VDD 2 Input Connect to VDD or VSS 8-A 5-A I/O Circuit Type 5-A I/O I/O Recommended Connections of Unused Pins Input: Connect to VDD Output: Leave open 18 Data Sheet U11680EJ2V0DS00 PD784907, 784908 Table 6-1. Types of Pin I/O Circuits and Recommended Connections of Unused Pins (2/2) Pin Name RESET TEST XT2 XT1 PWM0, PWM1 RX TX AVREF1 AVSS AVDD Connect to VDD 3 1 3 -- I/O Circuit Type 2 1 -- -- -- Input Output Input Output -- I/O Input Connect directly to VSS Leave open Connect to VSS Leave open Connect to VDD or VSS Leave open Connect to VSS Recommended Connections of Unused Pins -- Caution Connect an I/O pin, whose input/output mode is undefined, to VDD via a resistor of several 10 k (especially if the voltage on the reset input pin rises higher than the low level input at power on or when the mode is being switched between input and output by software). Remark Since type numbers are commonly used in the 78K Series, these numbers are not always serial in each product (some circuits are not included). Data Sheet U11680EJ2V0DS00 19 PD784907, 784908 Figure 6-1. I/O Circuits for Pins Type 1 Type 4 VDD VDD P IN N Data P OUT Output disable N Push-pull output which can output high impedance (both the positive and negative channels are off.) Type 2 Type 5-A VDD Pull-up enable IN P VDD P IN/OUT Data Schmitt trigger input with hysteresis characteristics Output disable Input enable N Type 2-A VDD Type 8-A VDD Pull-up enable Data IN Output disable N P Pull-up enable P VDD P IN/OUT Schmitt trigger input with hysteresis characteristics Type 3 Type 10-A VDD Pull-up enable VDD Data P IN/OUT N VDD P-ch Data N-ch OUT P Open drain Output disable 20 Data Sheet U11680EJ2V0DS00 PD784907, 784908 Type 20 Data VDD P IN/OUT Output disable Comparator + - VREF (Threshold voltage) Input enable P N N Data Sheet U11680EJ2V0DS00 21 PD784907, 784908 7. CPU ARCHITECTURE 7.1 Memory Space A memory space of 1 Mbyte can be accessed. By using a LOCATION instruction, the mode for mapping internal data areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be executed after a reset, and can be used only once. (1) When the LOCATION 0 instruction is executed * Internal memory The internal data area and internal ROM area are mapped as follows: Part Number Internal Data Area 0F100H to 0FFFFH 0EE00H to 0FFFFH Internal ROM Area 00000H to 0F0FFH 10000H to 17FFFH 00000H to 0FDFFH 10000H to 1FFFFH PD784907 PD784908 Caution The following internal ROM areas, existing at the same addresses as the internal data areas, cannot be used when the LOCATION 0 instruction is executed: Part Number Unusable Area 0F100H to 0FFFFH (3,840 bytes) 0EE00H to 0FFFFH (4,608 bytes) PD784907 PD784908 * External memory The external memory is accessed in external memory expansion mode. (2) When the LOCATION 0FH instruction is executed * Internal memory The internal data area and internal ROM area are mapped as follows: Part Number Internal Data Area FF100H to FFFFFH FEE00H to FFFFFH Internal ROM Area 00000H to 17FFFH 00000H to 1FFFFH PD784907 PD784908 * External memory The external memory is accessed in external memory expansion mode. 22 Data Sheet U11680EJ2V0DS00 Figure 7-1. PD784907 Memory Map When the LOCATION 0 instruction is executed F FF F FH 0 FEF FH General-purpose registers (128 bytes) 0 FE 8 0H 0 FE 7 FH Internal ROM (32,768 bytes) Special function registers (SFRs) Note 1 When the LOCATION 0FH instruction is executed F F F F F F F F FFFH FDFH FD0H F00H Special function registers (SFRs) Note 1 (256 bytes) External memory (928 Kbytes)Note 1 F FEF FH F FEF FH Internal RAM (3,584 bytes) 1 8 0 0 0H 1 7 F F FH 1 0 0 0 0H 0 FF F FH 0 FFDFH 0 FFD0H 0 FF 0 0H 0 FEF FH F FE 8 0H F FE 7 FH F FE 3 9H F FE 0 6H F FD0 0H F FCF FH F F 1 0 0H 1 7 F F FH Note 2 F F 1 0 0H F F 0 F FH 0 FE 3 9H Macro service control 0 FE 0 6H word area (42 bytes) Data area (512 bytes) 0 FD0 0H 0 FCF FH 0 F 1 0 0H 1 7FFFH 1 0000H (256 bytes) Data Sheet U11680EJ2V0DS00 Internal RAM (3,584 bytes) 0 F 1 0 0H 0 F 0 F FH Program/data area (3,072 bytes) External memory (946,432 bytes)Note 1 0 F 0 F FH 0 1 0 0 0H 0 0 F F FH Internal ROM (61,696 bytes) Note 4 Program/data areaNote 3 CALLF entry area (2 Kbytes) 0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH CALLT table area 0 0 0 4 0H (64 bytes) 0 0 0 3 FH Vector table area 0 0 0 0 0H (64 bytes) 1 8 0 0 0H 1 7 F F FH PD784907, 784908 Internal ROM (96 Kbytes) 0 0 0 0 0H Note 4 0 0 0 0 0H Notes 1. Accessed in external memory expansion mode. 2. This 3,840-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed. 3. When the LOCATION 0 instruction is executed: 94,464 bytes When the LOCATION 0FH instruction is executed: 98,304 bytes 4. Base area and entry area based on a reset or interrupt. However, internal RAM is not used as a reset entry area. 23 24 FF F F FH When the LOCATION 0 instruction is executed External memory (896 Kbytes)Note 1 2 0 0 0 0H 1F F F FH 1 0 0 0 0H 0F F F FH 0F FDFH 0F FD0H 0F F 0 0H 0FEF FH Internal ROM (65,536 bytes) Special function registers (SFRs) Note 1 Figure 7-2. PD784908 Memory Map When the LOCATION 0FH instruction is executed FF FF FF FF FFFH F D F H Special function registers (SFRs) F D 0 H Note 1 (256 bytes) F00H 0FEF FH General-purpose registers (128 bytes) 0FE 8 0H 0FE 7 FH 0FE 3 9H Macro service control 0FE 0 6H word area (42 bytes) 0FD0 0H 0FCF FH 0EE 0 0H 1FFFFH 10000H Note 2 FFEF FH FFEF FH Internal RAM (4,352 bytes) FFE 8 0H FFE 7 FH FFE 3 9H FFE 0 6H FFD0 0H FFCF FH FEE 0 0H 1F F F FH FEE 0 0H FEDF FH (256 bytes) Data area (512 bytes) Program/data area (3,840 bytes) Data Sheet U11680EJ2V0DS00 Internal RAM (4,352 bytes) 0EE 0 0H 0EDF FH External memory (912,896 bytes)Note 1 Internal ROM (60,928 bytes) Note 4 0 0 0 0 0H 0EDF FH Program/data areaNote 3 0 1 0 0 0H 0 0 F F FH CALLF entry area (2 Kbytes) 0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH CALLT table area 0 0 0 4 0H (64 bytes) 0 0 0 3 FH Vector table area 0 0 0 0 0H (64 bytes) 2 0 0 0 0H 1F F F FH Internal ROM (128 Kbytes) 0 0 0 0 0H Note 4 PD784907, 784908 Notes 1. Accessed in external memory expansion mode. 2. This 4,608-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed. 3. When the LOCATION 0 instruction is executed: 126,464 bytes When the LOCATION 0FH instruction is executed: 131,072 bytes 4. Base area and entry area based on a reset or interrupt. However, internal RAM is not used as a reset entry area. PD784907, 784908 7.2 7.2.1 CPU Registers General-purpose registers A set of general-purpose registers consists of sixteen 8-bit general-purpose registers. Two 8-bit general-purpose registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers, when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers. Eight banks of this register set are provided. The user can switch between banks by software or the context switching function. General-purpose registers other than the V, U, T, and W registers used for address extension are mapped onto internal RAM. Figure 7-3. General-Purpose Register Format A (R1) AX (RP0) B (R3) BC (RP1) R5 RP2 R7 RP3 V VVP (RG4) U T W R9 VP (RP4) X (R0) C (R2) R4 R6 R8 R11 R10 UUP (RG5) UP (RP5) D (R13) E (R12) TDE (RG6) DE (RP6) H (R15) L (R14) WHL (RG7) HL (RP7) The character strings enclosed in parentheses represent absolute names. 8 banks Caution By setting the RSS bit of PSW to 1, R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers, respectively. However, this function must be used only when using programs for the 78K/III series. Data Sheet U11680EJ2V0DS00 25 PD784907, 784908 7.2.2 Control registers (1) Program counter (PC) This register is a 20-bit program counter. The program counter is automatically updated by program execution. Figure 7-4. Format of Program Counter (PC) 19 PC 0 (2) Program Status Word (PSW) This register holds the CPU state. The program status word is automatically updated by program execution. Figure 7-5. Format of Program Status Word (PSW) 15 PSWH PSW 7 PSWL S 6 Z 5 RSS Note 14 RBS2 13 RBS1 12 RBS0 11 10 9 8 UF 4 AC 3 IE 2 P/V 1 0 0 CY Note This flag is used to maintain compatibility with the 78K/III Series. This flag must be set to 0 when programs for the 78K/III Series are not being used. (3) Stack pointer (SP) This register is a 24-bit pointer for holding the start address of the stack. The higher 4 bits must be set to 0. Figure 7-6. Format of Stack Pointer (SP) 23 SP 0 0 0 20 0 0 26 Data Sheet U11680EJ2V0DS00 PD784907, 784908 7.2.3 Special function registers (SFRs) The special function registers are registers with special functions such as mode registers and control registers for built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H and 0FFFFHNote. Note On execution of the LOCATION 0 instruction. FFF00H to FFFFFH when the LOCATION 0FH instruction is executed. Caution Do not access an address in this area where no SFR is allocated, as the PD784908 may be placed in the deadlock state. The deadlock state can be cleared only by a reset. Table 7-1 lists the special function registers (SFRs). The symbols of the table columns are explained below. * Symbol .................................... Symbol indicating an on-chip SFR. The symbols listed in the table are reserved words for the NEC assembler (RA78K4). In the C compiler (CC78K4), the symbols can be used as sfr variables with the #pragma sfr command. * R/W ......................................... Indicates whether the SFR is read-only, write-only, or read/write. R/W: Read/write R: W: Read-only. Write-only. * Bit units for manipulation ....... Indicates the maximum number of bits that can be manipulated whenever an SFR is manipulated. An SFR that supports 16-bit manipulation can be described in the sfrp operand. For address specification, an even-numbered address must be specified. An SFR that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction. * After reset ............................... Indicates the state of the register when the RESET signal has been input. Data Sheet U11680EJ2V0DS00 27 PD784907, 784908 Table 7-1. Special Function Registers (SFRs) (1/5) Address Note Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit 0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF09H 0FF0AH 0FF0EH 0FF0FH 0FF10H 0FF12H 0FF14H 0FF15H 0FF16H 0FF17H 0FF18H 0FF19H 0FF1AH 0FF1BH 0FF1CH 0FF1DH 0FF20H 0FF21H 0FF23H 0FF24H 0FF25H 0FF26H 0FF27H 0FF29H 0FF2AH 0FF2EH 0FF30H 0FF31H 0FF32H 0FF33H Port 0 buffer register H Compare register (timer/counter 0) Capture/compare register (timer/counter 0) Compare register L (timer/counter 1) Compare register H (timer/counter 1) Capture/compare register L (timer/counter 1) Capture/compare register H (timer/counter 1) Compare register L (timer/counter 2) Compare register H (timer/counter 2) Capture/compare register L (timer/counter 2) Capture/compare register H (timer/counter 2) Compare register L (timer 3) Compare register H (timer 3) Port 0 mode register Port 1 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 7 mode register Port 9 mode register Port 10 mode register Real-time output port control register Capture/compare control register 0 Timer output control register Capture/compare control register 1 Capture/compare control register 2 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 9 Port 10 P0 P1 P2 P3 P4 P5 P6 P7 P9 P10 Port 0 buffer register L P0L P0H CR00 CR01 CR10 CR10W -- CR11 CR11W -- CR20 CR20W -- CR21 CR21W -- CR30 CR30W -- PM0 PM1 PM3 PM4 PM5 PM6 PM7 PM9 PM10 RTPC CRC0 TOC CRC1 CRC2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10H 00H 10H 00H FFH -- -- -- -- -- -- R R/W R/W 8 bits 16 bits -- -- -- -- -- -- -- -- -- -- -- -- 00H Undefined Undefined After Reset Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 28 Data Sheet U11680EJ2V0DS00 PD784907, 784908 Table 7-1. Special Function Registers (SFRs) (2/5) AddressNote Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation After Reset 1 bit 8 bits 16 bits -- 0000H 0FF36H 0FF38H 0FF39H 0FF3AH 0FF3BH 0FF41H 0FF43H 0FF4AH 0FF4EH 0FF4FH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF5CH 0FF5DH 0FF5EH 0FF5FH 0FF68H 0FF6AH 0FF6CH 0FF6FH 0FF70H 0FF71H 0FF72H 0FF74H 0FF7DH 0FF80H 0FF82H Capture register (timer/counter 0) Capture register L (timer/counter 1) Capture register H (timer/counter 1) Capture register L (timer/counter 2) Capture register H (timer/counter 2) Port 1 mode control register Port 3 mode control register Port 10 mode control register Register L for optional pull-up resistor Register H for optional pull-up resistor Timer register 0 CR02 CR12 CR12W -- CR22 CR22W -- PMC1 PMC3 PMC10 PUOL PUOH TM0 R -- -- -- -- -- -- -- -- -- -- -- -- 00H R/W R -- -- -- -- -- -- 0000H Timer register 1 TM1 -- TM1W -- Timer register 2 TM2 -- TM2W -- -- -- Timer register 3 TM3 -- TM3W -- -- R/W -- -- -- -- -- -- -- -- R R/W -- -- -- -- -- -- -- -- -- -- -- -- -- 00H -- 05H 00H Undefined 11H 00H 11H 00H 00H Undefined 00H Prescaler mode register 0 Timer control register 0 Prescaler mode register 1 Timer control register 1 A/D converter mode register A/D conversion result register A/D current cut selection register Clock timer mode register PWM control register PWM prescaler register PWM modulo register 0 PWM modulo register 1 One-shot pulse output control register Clocked serial interface mode register 3 Clocked serial interface mode register PRM0 TMC0 PRM1 TMC1 ADM ADCR IEAD WM PWMC PWPR PWM0 PWM1 OSPC CSIM3 CSIM Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. Data Sheet U11680EJ2V0DS00 29 PD784907, 784908 Table 7-1. Special Function Registers (SFRs) (3/5) Address Note Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit 8 bits 16 bits -- -- -- -- -- -- R -- -- -- W R/W R W R/W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- R R/W -- -- -- After Reset 0FF84H 0FF85H 0FF86H 0FF88H 0FF89H 0FF8AH 0FF8BH 0FF8CH Clocked serial interface mode register 1 Clocked serial interface mode register 2 Serial shift register Asynchronous serial interface mode register Asynchronous serial interface mode register 2 Asynchronous serial interface status register Asynchronous serial interface status register 2 Serial receive buffer: UART0 Serial transmission shift register: UART0 Serial shift register: IOE1 CSIM1 CSIM2 SIO ASIM ASIM2 ASIS ASIS2 RXB TXS SIO1 RXB2 TXS2 SIO2 SIO3 BRGC BRGC2 INTM0 INTM1 SCS0 ISPR IMC MK0L MK0 MK0H MK1L MK1 MK1H BCR UAR SAR PAR CDR DLR R/W 00H Undefined 00H Undefined 0FF8DH Serial receive buffer: UART2 Serial transmission shift register: UART2 Serial shift register: IOE2 0FF8EH 0FF90H 0FF91H 0FFA0H 0FFA1H 0FFA4H 0FFA8H 0FFAAH 0FFACH 0FFADH 0FFAEH 0FFAFH 0FFB0H 0FFB2H 0FFB4H 0FFB6H 0FFB8H 0FFB9H Serial shift register 3: IOE3 Baud rate generator control register Baud rate generator control register 2 External interrupt mode register 0 External interrupt mode register 1 Sampling clock selection register In-service priority register Interrupt mode control register Interrupt mask register 0L Interrupt mask register 0H Interrupt mask register 1L Interrupt mask register 1H Bus control register Unit address register Slave address register Partner address register Control data register Telegraph length register 00H 80H FFFFH FFFFH -- -- -- R R/W -- -- -- -- -- -- -- -- 00H 0000H 01H Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 30 Data Sheet U11680EJ2V0DS00 PD784907, 784908 Table 7-1. Special Function Registers (SFRs) (4/5) AddressNote Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit 8 bits 16 bits -- -- -- -- -- -- R/W -- -- Note 2 Note 2 After Reset 0FFBAH 0FFBBH 0FFBCH 0FFBDH 0FFBEH 0FFBFH 0FFC0H 0FFC2H 0FFC4H 0FFC5H 0FFC6H 0FFC7H 0FFC8H 0FFCCH 0FFCDH 0FFCFH 0FFD0H to 0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFECH 0FFEDH 0FFEEH Data register Unit status register Interrupt status register Slave status register Success count register Communication count register Standby control register Watchdog timer mode register Memory expansion mode register Hold mode register Clock output mode register Programmable wait control register 1 Programmable wait control register 2 Refresh mode register Refresh area specification register DR USR ISR SSR SCR CCR STBC WDM MM HLDM CLOM PWC1 PWC2 RFM RFA R/W R R/W R -- 00H 41H 01H 20H 30H 00H 20H 00H -- -- -- -- -- -- -- -- -- -- -- AAH AAAAH -- -- -- -- -- -- 00H Oscillation stabilization time specification register OSTS External SFR area -- Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTC00) Interrupt control register (INTC01) Interrupt control register (INTC10) Interrupt control register (INTC11) Interrupt control register (INTC20) Interrupt control register (INTC21) Interrupt control register (INTC30) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTAD) Interrupt control register (INTSER) PIC0 PIC1 PIC2 PIC3 CIC00 CIC01 CIC10 CIC11 CIC20 CIC21 CIC30 PIC4 PIC5 ADIC SERIC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 43H Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 2. A write operation can be performed only with special instructions MOV STBC,#byte and MOV WDM,#byte. Other instructions cannot perform a write operation. Data Sheet U11680EJ2V0DS00 31 PD784907, 784908 Table 7-1. Special Function Registers (SFRs) (5/5) AddressNote Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation 1 bit 8 bits 16 bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- After Reset 0FFEFH Interrupt control register (INTSR) Interrupt control register (INTCSI1) SRIC CSIIC1 STIC CSIIC SERIC2 SRIC2 CSIIC2 STIC2 IEIC1 IEIC2 WIC CSIIC3 IMS R/W 43H 0FFF0H 0FFF1H 0FFF2H 0FFF3H Interrupt control register (INTST) Interrupt control register (INTCSI) Interrupt control register (INTSER2) Interrupt control register (INTSR2) Interrupt control register (INTCSI2) 0FFF4H 0FFF6H 0FFF7H 0FFF8H 0FFF9H 0FFFCH Interrupt control register (INTST2) Interrupt control register (INTIE1) Interrupt control register (INTIE2) Interrupt control register (INTW) Interrupt control register (INTCSI3) Internal memory size switching registerNote 2 FFH Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 2. A write to this register is meaningful only for the PD78P4908. 32 Data Sheet U11680EJ2V0DS00 PD784907, 784908 8. PERIPHERAL HARDWARE FUNCTIONS 8.1 Ports The ports shown in Figure 8-1 are provided to make various control operations possible. Table 8-1 shows the functions of the ports. When inputting to port 0 to port 6, port 9, and port 10, an on-chip pull-up resistor can be specified by software. Figure 8-1. Port Configuration P00 Port 0 P07 P10 Port 1 P17 P20 to P27 8 Port 2 P30 Port 3 P37 P40 Port 4 P47 P50 Port 5 P57 P60 Port 6 P97 P100 Port 10 P107 P77 P67 P70 Port 7 P90 Port 9 Data Sheet U11680EJ2V0DS00 33 PD784907, 784908 Table 8-1. Port Functions Port Name Port 0 Pin Name P00 to P07 Function * Input or output mode can be specified in 1-bit units * Operable as 4-bit real-time outputs (P00 to P03, P04 to P07) * Can drive transistors * Input or output mode can be specified in 1-bit units * Can drive LEDs Port 2 Port 3 P20 to P27 P30 to P37 * Input port * Input or output mode can be specified in 1-bit units * Either pin P32/SCK0 or P33/SO0 can be set as the N-ch open drain. * Input or output mode can be specified in 1-bit units * Can drive LEDs * Input or output mode can be specified in 1-bit units * Can drive LEDs * Input or output mode can be specified in 1-bit units * Input or output mode can be specified in 1-bit units * Input or output mode can be specified in 1-bit units Port 10 P100 to P107 * Input or output mode can be specified in 1-bit units * Either pin P105/SCK3 or P107/SO3 can be set as the N-ch open drain. All port pins in input mode In 6-bit units (P22 through P27) All port pins in input mode Specification of Pull-up Resistor Connection by Software All port pins in input mode Port 1 P10 to P17 All port pins in input mode Port 4 P40 to P47 All port pins in input mode Port 5 P50 to P57 All port pins in input mode Port 6 Port 7 Port 9 P60 to P67 P70 to P77 P90 to P97 All port pins in input mode -- All port pins in input mode 34 Data Sheet U11680EJ2V0DS00 PD784907, 784908 8.2 Clock Generator A circuit for generating the clock signal required for operation is provided. The clock generator has a frequency divider. If high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider to reduce the current consumption. Figure 8-2. Block Diagram of Clock Generator Clock-synchronized 3-wire serial I/O (CSI) Asynchronous serial I/O (UART/IOE) INTP0 noise eliminator Oscillation settling timer STBC.4, 5 Timer/counter Oscillator X2 fXX 1/2 1/2 1/2 fXX/8 X1 Selector fXX/4 fXX/2 fCLK CPU Peripheral circuits STBC.7 1 0 Selector Operation clock of the IEBus controllerNote Watch clock Watch timer Main clock INTW interrupt signal Note Set bit 7 of the standby control register (STBC) to 1. Remark fXX: Oscillator frequency or external clock input frequency fCLK: Internal operating frequency Data Sheet U11680EJ2V0DS00 35 PD784907, 784908 Figure 8-3. Examples of Using Oscillator (1) Crystal/ceramic oscillation PD784908 VSS X1 X2 (2) External clock * When EXTC bit of OSTS = 1 PD784908 X1 X1 * When EXTC bit of OSTS = 0 PD784908 PD74HC04, etc. X2 Open X2 Caution When using the clock generator, wire in the area enclosed by the broken lines to avoid adverse influence from capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern in which a high current flows. * Do not fetch signals from the oscillator. 36 Data Sheet U11680EJ2V0DS00 PD784907, 784908 Compared with the main system clock oscillator, the watch clock oscillator, which is a low-gain circuit designed to reduce current consumption, is more likely to cause noise-induced malfunctions. Therefore, special care should be taken when using the watch clock oscillator. The microcontroller can operate normally only when the oscillation is normal and stable. If a high-precision oscillator frequency is required, consult with the oscillator manufacturer. Figure 8-4. Notes on Connecting the Oscillator PD784908 X2 X1 VSS Cautions 1. Place the oscillator as close as possible to pins X1 and X2 (XT1 and XT2). 2. Do not let other signal lines cross that part of the circuit enclosed in broken lines. Data Sheet U11680EJ2V0DS00 37 PD784907, 784908 8.3 Real-Time Output Port The real-time output port outputs data stored in the buffer, synchronized with a timer/counter 1 match interrupt or external interrupt. Thus, pulse output that is free of jitter can be obtained. Therefore, the real-time output port is best suited to applications (such as open-loop control over stepping motors) where an arbitrary pattern is output at arbitrary intervals. As shown in Figure 8-5, the real-time output port is built around port 0 and the port 0 buffer register (P0H, P0L). Figure 8-5. Block Diagram of Real-Time Output Port Internal bus 8 Real-time output port control register (RTPC) INTP0 (externally) INTC10 (from timer/counter 1) INTC11 (from timer/counter 1) 4 4 Port 0 buffer register P0H P0L 8 Output trigger control circuit 4 4 Output latch (P0) P07 P00 38 Data Sheet U11680EJ2V0DS00 PD784907, 784908 8.4 Timers/Counters Three timer/counter units and one timer unit are incorporated. Moreover, because seven interrupt requests are supported, these timers/counters can be used as seven timer/ counter units. Table 8-2. Timers/Counters Operation Name Timer/Counter 0 Item Count width 8 bits 16 bits Operating mode Interval timer External event counter One-shot timer Function Timer output Toggle output PWM/PPG output One-shot pulse outputNote Real-time output Pulse width measurement Number of interrupt requests -- 1 input 2 1 input 2 -- 2 ch -- -- -- -- -- -- -- 2 inputs 2 2 ch 2 ch 2 ch 2 ch 1 ch -- -- -- -- -- -- -- -- 1 -- Timer/Counter 1 Timer/Counter 2 Timer 3 Note The one-shot pulse output function makes the level of a pulse output active by software, and makes the level of a pulse output inactive by hardware (interrupt request signal). Note that this function differs from the one-shot timer function of timer/counter 2. Data Sheet U11680EJ2V0DS00 39 PD784907, 784908 Figure 8-6. Timer/Counter Block Diagram Timer/counter 0 Clear control Software trigger Selector fXX/4 Prescaler Timer register 0 (TM0) OVF Match Pulse output control Compare register (CR00) TO0 Compare register (CR01) Match TO1 INTP3 Edge detection Capture register (CR02) INTP3 INTC00 INTC01 Timer/counter 1 Clear control Selector fXX/4 Prescaler Event input Timer register 1 (TM1/TM1W) OVF Match Compare register (CR10/CR10W) INTP0 Edge detection Capture/compare register (CR11/CR11W) Match INTC10 To real-time output port INTC11 INTP0 Capture register (CR12/CR12W) Timer/counter 2 Clear control Selector fXX/4 Prescaler Timer register 2 (TM2/TM2W) OVF Pulse output control INTP2/CI Edge detection Compare register (CR20/CR20W) Match TO2 INTP2 Capture/compare register (CR21/CR21W) Match TO3 INTP1 Edge detection Capture register (CR22/CR22W) INTC20 INTC21 INTP1 Timer 3 fXX/4 Prescaler Timer register 3 (TM3/TM3W) Clear Compare register (CR30/CR30W) Match UART, CSI INTC30 Remark OVF: Overflow flag 40 Data Sheet U11680EJ2V0DS00 PD784907, 784908 8.5 Watch Timer As the count clock, either of two types of clock can be input to the watch timer: the main clock (6.29 MHz/12.58 MHz) or the watch clock (32.768 kHz). They can be selected using the control register. The watch clock is input to the watch timer only. It is not input to the CPU or other peripheral circuits. Therefore, the speed of CPU operation cannot be slowed by the watch clock. The watch timer generates interrupt signals (INTW), at 0.5-second intervalsNote, by dividing the count clock. At the same time, the watch timer sets the interrupt request flag (WIF) (where WIF refers to bit 7 of the interrupt control register (WIC)). By switching modes, the INTW generation interval can be changed to about 1 ms (fast-forward mode: normal operation speed x 512). When the main clock is selected as the count clock, the watch timer stops if in STOP or IDLE standby mode, but continues operating if in HALT standby mode. When the watch clock is selected as the count clock, the watch timer continues operating regardless of the standby mode. The operation of the watch clock oscillator is controlled by means of the watch timer mode register (WM). The watch timer of the PD784908 does not have a buzzer output function. Note After the operation is enabled, the time until first INTW generation is not 0.5 s. Table 8-3. Relationship between Count Clock and Watch Timer Operation Count Clock Selection Normal Operation Mode HALT mode Main clock Watch clock Operable Operable Operable Operable Standby Modes STOP mode Stopped Operable IDLE mode Stopped Operable The watch timer consists of a frequency divider which divides the count clock by 3 and a counter which divides the frequency output from the frequency divider by 214. As the count clock, select the signal obtained by dividing the internal system clock by 128 or that output by the watch clock oscillator. Figure 8-7. Watch Timer Block Diagram WM.3 Reset 123456789 Main clock fXX/128 Division by 3 10 11 12 13 14 Counter 0 Watch clock oscillator Counter 0 SEL 1 WM.2 1 SEL 0 INTW SEL 1 ON/OFF WM.7 WM.6 STBC.7 Main clock selection: 6.29 MHz 12.58 MHz Data Sheet U11680EJ2V0DS00 41 PD784907, 784908 8.6 PWM Output (PWM0, PWM1) Two channels of PWM (pulse width modulation) output circuitry with a resolution of 12 bits and a repetition frequency of 24.57 kHz (fCLK = 6.29 MHz) are incorporated. Low or high active level can be selected for the PWM output channels, independently of each other. This output is best suited to DC motor speed control. Figure 8-8. Block Diagram of PWM Output Unit Internal bus 16 (Modulo register) PWMn 15 8 87 4 Reload control 43 0 8 PWM control register (PWMC) fCLK Prescaler 8-bit down-counter Pulse control circuit 4-bit counter Output control PWMn (output pin) 1/256 Remark n = 0, 1 42 Data Sheet U11680EJ2V0DS00 PD784907, 784908 8.7 A/D Converter An analog/digital (A/D) converter having 8 multiplexed analog inputs (ANI0 through ANI7) is incorporated. The successive approximation system is used for conversion. The result of conversion is held in the 8-bit A/D conversion result register (ADCR). Thus, speedy high-precision conversion can be achieved. A/D conversion can be started in the following two ways: * Hardware start: Conversion is started by trigger input (INTP5). * Software start: Conversion is started by setting the bit of the A/D converter mode register (ADM). After conversion has started, one of the following modes can be selected: * Scan mode: Multiple analog inputs are selected sequentially to convert multiple pins. * Select mode: A single analog input is selected at all times to enable conversion data to be obtained continuously. ADM is used to specify the above modes, as well as the termination of conversion. When the result of conversion is transferred to ADCR, an interrupt request (INTAD) is generated. Using this feature, the results of conversion can be continuously transferred to memory by the macro service. Cautions 1. For this product, apply the same voltage as the power supply voltage (AVDD) to the reference voltage input pin (AVREF1). 2. When port 7 is used as both an output port and A/D input line, do not manipulate the output port while A/D conversion is in progress. Figure 8-9. Block Diagram of A/D Converter Tap selector ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Input selector Sample and hold circuit Series resistor string AVDD Voltage comparator Connection control AVREF1 Successive approximation register (SAR) R/2 R R/2 AVSS A/D current cut selection register (IEAD) INTP5 Edge detection circuit Conversion trigger Control circuit INTAD Trigger enable 8 A/ D converter mode register (ADM) A/ D conversion result register (ADCR) 8 8 Internal bus Data Sheet U11680EJ2V0DS00 43 PD784907, 784908 8.8 Serial Interface Four independent serial interface channels are incorporated. * Asynchronous serial interface (UART)/3-wire serial I/O (IOE) x 2 * Synchronous serial interface (CSI) x 2 * 3-wire serial I/O (IOE) This makes it possible for communication with an external system and local communication within the system to be simultaneously executed (see Figure 8-10). Figure 8-10. Example of Serial Interface UART + 3-wire serial I/O + 2-wire serial I/O PD784908 (master) PD4711A [UART] Slave [3-wire serial I/O] SI SO SCK Port INT RS-232-C driver/receiver RxD TxD Port SO1 SI1 SCK1 INTPm Port Note VDD SI0 SO0 SCK0 INTPn Port Note VDD SB0 Slave SCK0 Port INT [2-wire serial I/O] Note Handshake line 44 Data Sheet U11680EJ2V0DS00 PD784907, 784908 8.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) Two serial interface channels, from which asynchronous serial interface mode and 3-wire serial I/O mode can be selected, are provided. (1) Asynchronous serial interface mode In this mode, 1-byte data is transferred or received after a start bit. A baud rate generator is incorporated to enable communication at a wide range of baud rates. A baud rate can be defined by dividing the frequency of a clock signal input to the ASCK pin. By using the baud rate generator, a baud rate conforming to the MIDI standard (31.25 kbps) can be obtained. Figure 8-11. Block Diagram of Asynchronous Serial Interface Mode Internal bus Receive buffer RXB, RXB2 RxD, RxD2 Receive shift register Transmission shift register TXS, TXS2 TxD, TxD2 INTSR, INTSR2 INTSER, INTSER2 Reception control parity check Transmission control parity bit addition INTST, INTST2 Baud rate generator 1/2m fXX ASCK, ASCK2 Selector 1/2 n+1 1/2m Remark fXX: Oscillating frequency or external clock input frequency n = 0 to 11 m = 16 to 30 Data Sheet U11680EJ2V0DS00 45 PD784907, 784908 (2) 3-wire serial I/O mode In this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data in synchronization with this clock. This mode is designed for communication with a device incorporating a conventional synchronous serial interface. Basically, three lines are used for communication: the serial clock line (SCK) and the two serial data lines (SI and SO). In general, a handshake line is required to check the state of communication. Figure 8-12. Block Diagram of 3-Wire Serial I/O Mode Internal bus Direction control circuit SIO1, SIO2 SI1, SI2 Shift register Output latch SO1, SO2 SCK1, SCK2 Serial clock counter Interrupt generator INTCSI1, INTCSI2 Serial clock control circuit Remark fXX: Oscillating frequency or external clock input frequency n = 0 to 11 m = 1, 16 to 30 46 Data Sheet U11680EJ2V0DS00 Selector 1/m 1/2n+1 fXX PD784907, 784908 8.8.2 Clocked serial interface (CSI) With this interface, the master device makes the serial clock active to start transmission, then transfers 1-byte data in synchronization with this clock. Figure 8-13. Block Diagram of Clocked Serial Interface Internal bus Selector SIn SIOn register CSIMn register SOn Serial clock counter INTCSIn SCKn Selector fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 Remark fXX: Oscillating frequency or external clock input frequency n = 0, 3 Data Sheet U11680EJ2V0DS00 47 PD784907, 784908 * 3-wire serial I/O mode This mode is designed for communication with a device incorporating a conventional clocked serial interface. Basically, three lines are used for communication: the serial clock line (SCKn) and serial data lines (SIn and SOn) (n = 0, 3). In general, a handshake line is required to check the state of communication. 8.9 Clock Output Function The frequency of the CPU clock signal can be divided and output from the system. Moreover, the port can be used as a 1-bit port. The ASTB pin is also used as the CLKOUT pin, so that when this function is used, the local bus interface cannot be used. Figure 8-14. Block Diagram of Clock Output Function fCLK fCLK/2 Selector fCLK/4 fCLK/8 fCLK/16 Output control CLKOUT Enable output Output level 48 Data Sheet U11680EJ2V0DS00 PD784907, 784908 8.10 Edge Detection Function The interrupt input pins (NMI, INTP0 through INTP5) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. Because these pins operate at the edge of the input signal, they have an edge-detection function incorporated. Moreover, a noise elimination function is also provided to prevent erroneous edge detection caused by noise. Table 8-4. Noise Elimination Method of Interrupt Input Pins Pin Name NMI INTP0 to INTP3 INTP4, INTP5 Detectable Edge Rising edge or falling edge Rising edge or falling edge, or both edges Noise Elimination Method Analog delay Clock samplingNote Analog delay Note INTP0 is used for sampling clock selection. 8.11 Watchdog Timer A watchdog timer is incorporated to detect a CPU runaway. The watchdog timer, if not cleared by software within a specified interval, generates a non-maskable interrupt request. Furthermore, once watchdog timer operation is enabled, it cannot be disabled by software. The user can specify whether priority is placed on an interrupt request based on the watchdog timer or on an interrupt request based on the NMI pin. Figure 8-15. Block Diagram of Watchdog Timer fCLK Timer fCLK/221 fCLK/220 Selector fCLK/219 fCLK/217 INTWDT Clear signal Data Sheet U11680EJ2V0DS00 49 PD784907, 784908 8.12 Simplified IEBus Controller A newly developed IEBus controller is incorporated into the PD784908. This IEBus controller has fewer functions than the IEBus interface function of previous product (incorporated into the 78K/0). Table 8-5 compares the previous product and the new, simplified IEBus interface. Table 8-5. Comparisons between Previous Product and Simplified IEBus Interface Item Communication mode Internal system clock Internal buffer size Previous Product (IEBus Incorporated into 78K/0) Modes 0 to 2 6.0 (6.29) MHz Transmission buffer 33 bytes (FIFO) Reception buffer 40 bytes (FIFO) Up to four frames can be received Processing before transmission start (data setting) Setting and control of each communication status Data write to the transmission buffer Data read from the reception buffer Transmission/reception data register 1 byte Simplified IEBus Fixed to mode 1 CPU processing Processing before transmission start (data setting) Setting and control of each communication status Data write processing for every byte Data read processing for every byte Transmission control such as slave status Control of multiple frames, remastering request Bit processing (modulation/demodulation, error detection) Field processing (generation, control) Detection of arbitration results Parity processing (generation, error detection) ACK/NACK automatic response Automatic data retransmitting Hardware processing Bit processing (modulation/demodulation, error detection) Field processing (generation, control) Detection of arbitration results Parity processing (generation, error detection) ACK/NACK automatic response Automatic data retransmitting Automatic remastering Transmission such as automatic slave status Reception of multiple frames 50 Data Sheet U11680EJ2V0DS00 PD784907, 784908 Figure 8-16. IEBus Controller CPU interface section 8 Internal register section 12 12 12 8 8 DLR(8) 8 DR(8) 8 USR(8) 8 ISR(8) 8 8 8 BCR(8) UAR(12) SAR(12) PAR(12) CDR(8) SSR(8) SCR(8) CCR(8) 8 12 12 12 8 8 8 8 8 8 8 8 Internal bus 8 RX 8 NF MPX TX/RX Conflict detector PSR (8 bits) 12-bit latch Interrupt control circuit 12 Comparator INT request (vector, macro service) TX MPX Parity error detector Interrupt control section ACK generator IEBus interface section CLK 5 Internal bus R/W Bit processing section Field processing section Data Sheet U11680EJ2V0DS00 51 PD784907, 784908 * Hardware configuration and functions The internal configuration of the IEBus consists mainly of the following six sections: * CPU interface section * Interrupt control section * Internal register section * Bit processing section * Field processing section * IEBus interface section 52 Data Sheet U11680EJ2V0DS00 PD784907, 784908 9. INTERRUPT FUNCTION The three types of interrupt request-response servicing, as shown in Table 9-1 below, can be selected by program. Table 9-1. Servicing of Interrupt Request Servicing Mode Vectored interrupt Context switching Servicing Agent Software Servicing Branches and executes a servicing routine (servicing is arbitrary). Automatically switches register banks, and branches and executes a servicing routine (servicing is arbitrary). Firmware Executes data transfer between memory and I/O (servicing is fixed). Saves to or restores from fixed area in the register bank. Maintained PC and PSW Contents Saves to and restores from the stack. Macro service 9.1 Interrupt Source Table 9-2 shows the interrupt sources available. As shown, interrupts are generated by 27 types of sources, execution of the BRK and BRKCS instructions, or an operand error. Four levels of interrupt servicing priority can be set. Priority levels can be set to nest control during interrupt servicing or to simultaneously generate interrupt requests. However, nested macro services are performed without suspension. When interrupt requests having the same priority level are generated, they are serviced according to the default priority (fixed) (see Table 9-2). Data Sheet U11680EJ2V0DS00 53 PD784907, 784908 Table 9-2. Interrupt Source Type Default Priority -- Source Name BRK instruction Instruction execution Trigger Internal/ Macro External Service -- -- Software BRKCS instruction Instruction execution Operand error When the MOV STBC,#byte, MOV WDM,#byte, or LOCATION instruction is executed, exclusive OR of the byte operand and byte does not produce FFH. Detection of edge input on the pin Watchdog timer overflow External Internal -- Non-maskable -- NMI WDT Maskable 0 (highest) INTP0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC20 INTC21 INTC30 INTP4 INTP5 INTAD INTSER INTSR INTCSI1 16 17 18 19 INTST INTCSI INTSER2 INTSR2 INTCSI2 20 21 22 23 INTST2 INTIE1 INTIE2 INTW Detection of edge input on the pin (TM1/TM1W capture trigger) External Detection of edge input on the pin (TM2/TM2W capture trigger) Detection of edge input on the pin (TM2/TM2W event counter input) Detection of edge input on the pin (TM0 capture trigger) TM0-CR00 match signal issued TM0-CR01 match signal issued TM1-CR10 match signal issued (in 8-bit operation mode) TM1W-CR10W match signal issued (in 16-bit operation mode) TM1-CR11 match signal issued (in 8-bit operation mode) TM1W-CR11W match signal issued (in 16-bit operation mode) TM2-CR20 match signal issued (in 8-bit operation mode) TM2W-CR20W match signal issued (in 16-bit operation mode) TM2-CR21 match signal issued (in 8-bit operation mode) TM2W-CR21W match signal issued (in 16-bit operation mode) TM3-CR30 match signal issued (in 8-bit operation mode) TM3W-CR30W match signal issued (in 16-bit operation mode) Detection of edge input on the pin Detection of edge input on the pin (A/D converter start conversion trigger) A/D converter processing completed (ADCR transfer) ASI0 reception error ASI0 reception completed or CSI1 transfer completed Internal External Internal -- ASI0 transmission completed CSI0 transfer completed ASI2 reception error ASI2 reception completed or CSI2 transfer completed -- ASI2 transmission completed IEBus data access request IEBus communication error and communication start/end Clock timer output CSI3 transfer completed 24 (lowest) INTCSI3 Remark ASI: Asynchronous serial interface CSI: Clocked serial interface 54 Data Sheet U11680EJ2V0DS00 PD784907, 784908 9.2 Vectored Interrupt When a branch to an interrupt servicing routine occurs, the vector table address corresponding to the interrupt source is used as the branch address. Interrupt servicing by the CPU consists of the following operations : * When branching: Saves the CPU status (PC and PSW contents) to the stack. * When returning: Restores the CPU status (PC and PSW contents) from the stack. To return control from the servicing routine to the main routine, the RETI instruction is used. The branch destination addresses must be within the range of 0 to FFFFH. Table 9-3. Vector Table Address Interrupt Source BRK instruction Operand error NMI WDT INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC20 INTC21 INTC30 INTP4 INTP5 INTAD INTSER INTSR INTCSI1 INTST INTCSI INTSER2 INTSR2 INTCSI2 INTST2 002EH 0026H 0028H 002AH 002CH Vector Table Address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H Interrupt Source NTIE1 INTIE2 INTW INTCSI3 Vector Table Address 0032H 0034H 0036H 0038H Data Sheet U11680EJ2V0DS00 55 PD784907, 784908 9.3 Context Switching When an interrupt request is generated, or when the BRKCS instruction is executed, a predetermined register bank is selected by the hardware. Then, a branch to a vector address stored in that register bank occurs. At the same time, the contents of the current program counter (PC) and program status word (PSW) are stacked in the register bank. The branch address must be within the range of 0 to FFFFH. Figure 9-1. Context Switching Operation When Interrupt Request Is Generated 0000B <7> Transfer Register bank n (n = 0-7) A B X C R4 R6 VP UP D H E L <3> Switching Register bank (0 to 7) PC19-16 PC15-0 <2>Save <6> Exchange R5 R7 (Bits 8 to 11 of temporary register) <5> Save V U Temporary register <1> Save T W between register banks (RBS0-RBS2 n) <4> RSS 0 IE 0 PSW 9.4 Macro Service The macro service function enables data transfer between memory and special function registers (SFRs) without requiring the intervention of the CPU. The macro service controller accesses both memory and SFRs within the same transfer cycle to directly transfer data without having to perform data fetch. Since the CPU status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is possible. Figure 9-2. Macro Service Read CPU Memory Write Macro service controller Write SFR Read Internal bus 56 Data Sheet U11680EJ2V0DS00 PD784907, 784908 9.5 Examples of Macro Service Applications (1) Serial interface transmission Transmit data storage buffer (memory) Data n Data n - 1 Data 2 Data 1 Internal bus TxD Transmit shift register TXS (SFR) Transmit control INTST Each time macro service request (INTST) is generated, the next transmit data is transferred from memory to TXS. When data n (last byte) has been transferred to TXS (that is, once the transmit data storage buffer becomes empty), vectored interrupt request (INTST) is generated. (2) Serial interface reception Receive data storage buffer (memory) Data n Data n - 1 Data 2 Data 1 Internal bus Receive buffer RXB (SFR) RxD Receive shift register Receive control INTSR Each time macro service request (INTSR) is generated, receive data is transferred from RXB to memory. When data n (last byte) has been transferred to memory (that is, once the receive data storage buffer becomes full), vectored interrupt request (INTSR) is generated. Data Sheet U11680EJ2V0DS00 57 PD784907, 784908 (3) Real-time output port INTC10 and INTC11 function as the output triggers for the real-time output ports. For these triggers, the macro service can simultaneously set the next output pattern and interval. Therefore, INTC10 and INTC11 can be used to independently control two stepping motors. They can also be applied to PWM and DC motor control. Output pattern profile (memory) Pn Pn-1 Output timing profile (memory) Tn Tn-1 P2 P1 T2 T1 Internal bus Internal bus Match (SFR) P0L INTC10 Output latch P00 to P03 TM1 CR10 (SFR) Each time macro service request (INTC10) is generated, a pattern and timing data are transferred to the buffer register (P0L) and compare register (CR10), respectively. When the contents of timer register 1 (TM1) and CR10 match, another INTC10 is generated, and the P0L contents are transferred to the output latch. When Tn (last byte) is transferred to CR10, vectored interrupt request (INTC10) is generated. For INTC11, the same operation as that performed for INTC10 is performed. 58 Data Sheet U11680EJ2V0DS00 PD784907, 784908 10. LOCAL BUS INTERFACE The local bus interface enables the connection of external memory and I/O devices (memory mapped I/O) and supports a 1-Mbyte memory space (see Figure 10-1). Figure 10-1. Example of Local Bus Interface PD784908 A16 to A19 Decoder RD WR REFRQ Pseudo SRAM PROM PD27C1001A Kanji character generator PD24C1000 AD0 to AD7 Data bus ASTB Latch Address bus A8 to A15 Gate array for I/O expansion including Centronics interface circuit, etc. 10.1 Memory Expansion By adding external memory, program memory or data memory can be expanded, 256 bytes at a time, to approximately 1 Mbyte (seven steps). Data Sheet U11680EJ2V0DS00 59 PD784907, 784908 10.2 Memory Space The 1-Mbyte memory space is divided into eight spaces, each having a logical address. Each of these spaces can be controlled using the programmable wait and pseudo-static RAM refresh functions. Figure 10-2. Memory Space FFFFFH 512 Kbytes 80000H 7FFFFH 256 Kbytes 40000H 3FFFFH 128 Kbytes 20000H 1FFFFH 64 Kbytes 10000H 0FFFFH 16 Kbytes 0C000H 0BFFFH 16 Kbytes 08000H 07FFFH 16 Kbytes 04000H 03FFFH 16 Kbytes 00000H 60 Data Sheet U11680EJ2V0DS00 PD784907, 784908 10.3 Programmable Wait When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory space while the RD or WR signal is active. This prevents the overall system efficiency from being degraded even when memory devices having different access times are connected. In addition, an address wait function that extends the ASTB signal active period is provided to ensure the lapse of the address decode time. (This function is set for the entire space.) 10.4 Pseudo-Static RAM Refresh Function Refresh is performed as follows: * Pulse refresh A bus cycle is inserted where a refresh pulse is output on the REFRQ pin at regular intervals. When the memory space is divided into eight, and a specified area is being accessed, refresh pulses can also be output on the REFRQ pin as the memory is being accessed. This can prevent the refresh cycle from suspending normal memory access. * Power-down self-refresh In standby mode, a low-level signal is output on the REFRQ pin to maintain the contents of pseudo-static RAM. 10.5 Bus Hold Function A bus hold function is provided to facilitate connection to devices such as a DMA controller. When a bus hold request signal (HLDRQ) is received from an external bus master, the address bus, address/data bus, and ASTB, RD, and WR pins enter the high-impedance state, the bus hold acknowledge signal (HLDAK) is made active, and the bus is released to the external bus master as soon as the current bus cycle is completed. While the bus hold function is being used, the external wait and pseudo-static RAM refresh functions are disabled. Data Sheet U11680EJ2V0DS00 61 PD784907, 784908 11. STANDBY FUNCTION This function is to reduce the power consumption of the chip, and can be used in the following modes: * HALT mode: Stops the operating clock of the CPU. This mode is used in combination with the normal operation mode for intermittent operation to reduce the average power consumption. * IDLE mode: Stops the entire system with the oscillator continuing operation. The power consumption in this mode is close to that in the STOP mode. However, the time required to restore the normal program operation from this mode is almost the same as that from the HALT mode. * STOP mode: Stops the oscillator and thereby stops all the internal operations of the chip. Consequently, the power consumption is minimized with only leakage current flowing. These modes are programmable. The macro service can be started from the HALT mode. Figure 11-1. Standby Mode Status Transition Macro service request Program operation End of one operation End of macro service Macro service Wait for oscillation settling 1 ttli tion se Oscilla ses p time ela ng ut N re ice rv se ro ac M HALT (standby) inp Se IN NM TW N R t I, I otes ES IDL 1, ET E NT 3 P4 inp , IN ut TP 5i np ut No te IN NM TW N ot I, IN es 1, TP 3 4, IN T STOP (standby) IDLE (standby) Request for masked interrupt Notes 1. INTW, INTP4, and INTP5 are applied when not masked. 2. Only unmasked interrupt request 3. When the watch clock is operating Remark NMI is valid only for an external input. The watchdog timer cannot be used for the release of standby (STOP, HALT, or IDLE mode). 62 Data Sheet U11680EJ2V0DS00 En d P TO ut t S inp Se ET S RE P5 of on e op er at es t ion Int N t es qu t re u pt inp ru T LT er SE HA RE Set ot e 1 qu e2 ot PD784907, 784908 12. RESET FUNCTION When a low-level signal is input to the RESET pin, the internal hardware becomes initialize status (reset status). When the RESET input makes a low-to-high transition, the following data is loaded into the program counter (PC): * Low-order 8 bits of the PC: * High-order 4 bits of the PC: Contents of address 0000H 0 * Intermediate 8 bits of the PC: Contents of address 0001H The PC contents are used as a branch destination address, and program execution starts from that address. Therefore, a reset start can be performed from an arbitrary address. The contents of each register can be set by software, as necessary. The RESET input circuit incorporates a noise eliminator to prevent malfunctions caused by noise. This noise eliminator is an analog delay sampling circuit. Figure 12-1. Accepting Reset Delay Initialize PC Execute instruction of reset start address Delay Delay RESET (input) Internal reset signal Start reset End reset For power-on reset, the RESET signal must be held active until the oscillation stabilization time (approximately 40 ms) has elapsed. Figure 12-2. Power-On Reset Oscillation stabilization time Delay Execute instruction of reset start address Initialize PC VDD RESET (input) Internal reset signal End reset Data Sheet U11680EJ2V0DS00 63 PD784907, 784908 13. REGULATOR The PD784908 incorporates a regulator (a circuit which enables low-voltage operation) to reduce the current consumption of the device. To enable or disable the operation of this regulator, specify the input level of the REGOFF pin. To disable the operation of the regulator, input a high level signal to the REGOFF pin. To enable operation, input a low level signal to the REGOFF pin. When the regulator is turned on, the CPU enters low-power mode. It is recommended to operate this product using this regulator. To stabilize the regulator output voltage, connect a capacitor (of about 1F) to the REGC pin (stabilizing capacitor connection pin). When the regulator is stopped, apply the same level as VDD to the REGC pin. Figure 13-1 is a block diagram of the regulator's peripheral circuits. Figure 13-1. Regulator Peripheral Circuits REGOFF Low level: Regulator is turned on. High level: Regulator is turned off. VDD Regulator Internal power supply voltage (Supplies to the CPU and peripheral circuits.) Stops oscillation. STBC.7 REGC 1 F * Processing for the REGC pin When the regulator is operating When the regulator is stopped Connect a capacitor to stabilize the regulator. Supply the power supply voltage. 64 Data Sheet U11680EJ2V0DS00 PD784907, 784908 14. INSTRUCTION SET (1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA Table 14-1. Instruction List by 8-Bit Addressing 2nd operand #byte A r r' 1st operand A (MOV) (MOV) MOV XCH (MOV)Note 6 MOV (XCH)Note 6 (XCH) (MOV) (XCH) saddr saddr' sfr !addr16 !!addr24 mem [saddrp] [%saddrg] MOV XCH ADDNote 1 r3 PSWL PSWH MOV (MOV) (XCH) (ADD)Note 1 ROR Note 3 MULU DIVUW INC DEC saddr MOV (MOV)Note 6 MOV MOV ADDNote 1 sfr MOV MOV MOV INC DEC DBNZ PUSH POP CHKL CHKLA !addr16 !!addr24 mem [saddrp] [%saddrg] mem3 ROR4 ROL4 r3 PSWL PSWH B, C STBC, WDM [TDE+] [TDE-] MOV (MOV) (ADD)Note 1 MOVMNote 4 MOVBKNote 5 DBNZ MOV MOV MOV (MOV) ADDNote 1 MOV ADDNote 1 MOV [WHL+] [WHL-] n None Note 2 ADDNote 1 (XCH) (ADD)Note 1 (ADD)Note 1 (ADD)Notes 1, 6 (ADD)Note 1 ADDNote 1 r MOV (MOV) MOV XCH MOV XCH MOV XCH MOV XCH ADDNote 1 (XCH) (ADD)Note 1 ADDNote 1 ADDNote 1 ADDNote 1 ADDNote 1 (ADD)Note 1 ADDNote 1 XCH ADDNote 1 (ADD)Note 1 ADDNote 1 Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD. 2. There is no second operand, or the second operand is not an operand address. 3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR. 4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM. 5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK. 6. When saddr is saddr2 with this combination, an instruction with a short code exists. Data Sheet U11680EJ2V0DS00 65 PD784907, 784908 (2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 14-2. Instruction List by 16-Bit Addressing 2nd operand #word AX rp rp' 1st operand AX (MOVW) (MOVW) (MOVW) (XCHW) (MOVW)Note 3 MOVW (MOVW) XCHW saddrp saddrp' sfrp !addr16 !!addr24 mem [saddrp] [%saddrg] MOVW XCHW (MOVW) (XCHW) [WHL+] byte n NoneNote 2 ADDWNote 1 (XCHW) (XCHW)Note 3 (XCHW) (ADD)Note 1 (ADDW) Note 1 (ADDW)Notes 1,3 (ADDW)Note 1 rp MOVW ADDWNote 1 (MOVW) (XCHW) MOVW XCHW MOVW XCHW MOVW XCHW MOVW SHRW SHLW MULWNote 4 INCW DECW INCW DECW (ADDW)Note 1 ADDWNote 1 ADDWNote 1 ADDWNote 1 saddrp MOVW (MOVW)Note 3 MOVW MOVW ADDWNote 1 sfrp MOVW MOVW MOVW ADDWNote 1 (ADDW)Note 1 ADDWNote 1 XCHW PUSH POP MOVTBLW ADDWNote 1 (ADDW)Note 1 ADDWNote 1 !addr16 !!addr24 mem [saddrp] [%saddrg] PSW MOVW MOVW (MOVW) MOVW PUSH POP SP ADDWG SUBWG post PUSH POP PUSHU POPU [TDE+] byte (MOVW) SACW MACW MACSW Notes 1. SUBW and CMPW are the same as ADDW. 2. There is no second operand, or the second operand is not an operand address. 3. When saddrp is saddrp2 with this combination, an instruction with a short code exists. 4. MULUW and DIVUX are the same as MULW. 66 Data Sheet U11680EJ2V0DS00 PD784907, 784908 (3) 24-bit instructions (The instructions in parentheses are combinations realized by describing WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 14-3. Instruction List by 24-Bit Addressing 2nd operand 1st operand WHL (MOVG) (ADDG) (SUBG) rg MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) #imm24 WHL rg rg' (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH POP saddrg !!addr24 mem1 [%saddrg] SP MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] SP NoneNote Note There is no second operand, or the second operand is not an operand address. Data Sheet U11680EJ2V0DS00 67 PD784907, 784908 (4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 14-4. Bit Manipulation Instruction List by Addressing 2nd operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit 1st operand CY !addr16.bit !!addr24.bit MOV1 AND1 OR1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BF BT BTCLR BFSET /saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit AND1 OR1 /!!addr24.bit NOT1 SET1 CLR1 NoneNote Note There is no second operand, or the second operand is not an operand address. 68 Data Sheet U11680EJ2V0DS00 PD784907, 784908 (5) Call/return instructions and branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 14-5. Instruction List by Call/Return and Branch Instruction Addressing Instruction address operand Basic instruction BCNote BR CALL BR CALL BR RETCS RETCSB Compound instruction BF BT BTCLR BFSET DBNZ CALL BR CALL BR CALL BR CALL BR CALL BR CALLF CALLF BRKCS BRK RET RETI RETB $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT EI, DI, SWRS Data Sheet U11680EJ2V0DS00 69 PD784907, 784908 15. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol VDD AVDD AVSS Input voltage Analog input voltage Output voltage Output current, low VI1 VAN VO IOL Per pin Total of P00 to P07, P30 to P37, P54 to P57, P60 to P67, and P100 to P107 pins Total of P10 to P17, P40 to P47, P50 to P53, P70 to P77, P90 to P97, PWM0, PWM1, and TX pins Output current, high IOH Per pin Total of P00 to P07, P30 to P37, P54 to P57, P60 to P67, and P100 to P107 pins Total of P10 to P17, P40 to P47, P50 to P53, P70 to P77, P90 to P97, PWM0, PWM1, and TX pins A/D converter reference input voltage Operating ambient temperature Storage temperature TA Tstg -40 to +85 -65 to +150 C C AVREF1 Conditions Ratings -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 AVSS - 0.3 to AVREF1 + 0.3 -0.3 to VDD + 0.3 10 50 Unit V V V V V V mA mA 50 mA -6 -30 mA mA -30 mA -0.3 to VDD + 0.3 V Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless otherwise specified, the characteristics of a alternate-function pin are the same as those of a port pin. 70 Data Sheet U11680EJ2V0DS00 PD784907, 784908 Operating Conditions * * * Operating ambient temperature (TA): -40C to +85C Power supply voltage and clock cycle time: see Figure 15-1. Selection of internal regulator (REGOFF pin: low-level input) Figure 15-1. Power Supply Voltage and Clock Cycle Time 10,000 4,000 Clock cycle time tCYK [ns] 1,000 Guaranteed operating range 159 100 79 10 0 1 2 3 4 5 Power supply voltage [V] 6 7 Capacitance (TA = 25C, VDD = VSS = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Conditions f = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX. 15 15 15 Unit pF pF pF Data Sheet U11680EJ2V0DS00 71 PD784907, 784908 Main Oscillator Characteristics (TA = -40 to +85C, VDD = 3.5 to 5.5 V, VSS = 0 V) Parameter Oscillator frequency Symbol fXX Conditions Ceramic resonator or crystal resonator MIN. 2 MAX. 12.58 Unit MHz Caution When using the clock generator, wire to avoid adverse influence from wiring capacitance. * * * * * Keep the wiring length as short as possible. Do not cross the wiring with other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. Make the ground point of the oscillator capacitor the same potential as VSS1. Do not ground the capacitor to a ground pattern in which a high current flows. Do not fetch signals from the oscillator. Remark Connect a 12.582912 MHz or 6.291456 MHz oscillator to operate the internal clock timer with the main clock. Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 3.5 to 5.5 V, VSS = 0 V) Parameter Oscillator frequency Oscillation stabilization time Oscillation hold voltage Watch timer operating voltage Symbol fXT tSXT Conditions Ceramic resonator or crystal resonator VDD = 4.5 to 5.5 V MIN. 32 TYP. 32.768 1.2 MAX. 35 2 10 VDDXT VDDW 3.5 3.5 5.5 5.5 Unit kHz s s V V 72 Data Sheet U11680EJ2V0DS00 PD784907, 784908 DC Characteristics (TA = -40 to +85C, VDD = AVDD = 3.5 to 5.5 V, VSS = AVSS = 0 V) (1/2) Parameter Input voltage, lowNote 5 Symbol VIL1 VIL2 VIL3 Input voltage, high VIH1 VIH2 VIH3 Output voltage, low VOL1 Conditions For pins other than Notes 1 and 2 For pins described in Note 1 VDD = 4.5 to 5.5 V For pins described in Note 2 For pins other than Notes 1 and 2 For pins described in Note 1 VDD = 4.5 to 5.5 V For pins described in Note 2 IOL = 20 A IOL = 100 A IOL = 2 mA VOL2 IOL = 8 mA For pins described in Note 4 VDD = 4.5 to 5.5 V IOH = -20 A IOH = -100 A IOH = -2 mA VOH2 VDD = 4.5 to 5.5 V IOH = -5 mA For pins described in Note 3 VDD - 0.1 VDD - 0.2 VDD - 0.4 VDD - 1.0 MIN. -0.3 -0.3 -0.3 0.7VDD 0.8VDD 2.2 TYP. MAX. 0.3VDD 0.2VDD +0.8 VDD + 0.3 VDD + 0.3 VDD + 0.3 0.1 0.2 0.4 1.0 Unit V V V V V V V V V V Output voltage, high VOH1 V V V V Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3, P107/SO3, XT1, XT2 2. P40/AD0 to P47/AD7, P50/A8 to P57/A15, P60/A16 to P67/REFRQ/HLDAK, P00 to P07 3. P00 to P07 4. P10 to P17, P40/AD0 to P47/AD7, P50/A8 to P57/A15 5. Other than pull-up resistors Data Sheet U11680EJ2V0DS00 73 PD784907, 784908 DC Characteristics (TA = -40 to +85C, VDD = AVDD = 3.5 to 5.5 V, VSS = AVSS = 0 V) (2/2) Parameter Input leakage current Symbol ILI1 ILI2 Output leakage current VDD supply currentNote ILO IDD1 0 V VO VDD Operation mode fXX = 12.58 MHz VDD = 4.0 to 5.5 V fXX = 6.29 MHz VDD = 3.5 to 5.5 V IDD2 HALT mode fXX = 12.58 MHz VDD = 4.0 to 5.5 V fCLK = fXX/8 (STBC = B1H) Peripheral operation stops. fXX = 6.29 MHz VDD = 3.5 to 5.5 V fCLK = fXX/8 (STBC = 31H) Peripheral operation stops. IDD3 IDLE mode fXX = 12.58 MHz VDD = 4.0 to 5.5 V fXX = 6.29 MHz VDD = 3.5 to 5.5 V Pull-up resistor RL VI = 0 V X1 and XT1 15 10 5 2.0 0 V VI VDD Conditions For pins other than X1 and XT1 X1 and XT1 MIN. TYP. MAX. 10 20 10 20 10 4.0 Unit A A A mA mA mA 1.2 2.4 mA 0.6 0.3 1.2 0.6 80 mA mA k Note These values are valid when the internal regulator is ON (REGOFF pin = L level). They do not include the AVDD and AVREF1 currents. 74 Data Sheet U11680EJ2V0DS00 PD784907, 784908 AC Characteristics (TA = -40 to +85C, VDD = AVDD = 3.5 to 5.5 V, AVSS = VSS = 0 V) (1) Read/write operation Parameter Address setup time (to ASTB) ASTB high-level width Address hold time (from ASTB) Address hold time (from RD) Delay from address to RD Address float time (from RD) Data input time from address Data input time from ASTB Data input time from RD Delay from ASTB to RD Data hold time (from RD) Address active time from RD Delay from RD to ASTB RD low-level width Delay from address to WR Address hold time (from WR) Delay from ASTB to data output Delay from WR to data output Delay from ASTB to WR Data setup time (to WR) Data hold time (from WR) Delay from WR to ASTB WR low-level width Symbol tSAST tWSTH tHSTLA tHRA tDAR tFRA tDAID tDSTID tDRID tDSTR tHRID tDRA tDRST tWRL tDAW tHWA tDSTOD tDWOD tDSTW tSODWR tHWOD tDWST tWWL VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V 0.5T - 9 (1.5 + n)T - 20 0.5T - 14 0.5T - 9 (1.5 + n)T - 25 31 99 26 31 94 VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V 0.5T - 2 0.5T - 9 (1.5 + n)T - 25 (1 + a)T - 5 0.5T - 14 0.5T + 15 VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V (2.5 + a + n)T - 37 (2 + n)T - 35 (1.5 + n)T - 40 0.5T - 9 31 0 38 31 94 74 26 55 15 VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V Conditions (0.5 + a)T - 11 (0.5 + a)T - 17 0.5T - 19 0.5T - 14 (1 + a)T - 5 MIN. 29 23 21 26 74 0 400 283 238 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remark T: a: n: tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.) 1 during address wait, otherwise, 0 number of wait states (n 0) Data Sheet U11680EJ2V0DS00 75 PD784907, 784908 (2) External wait timing Parameter WAIT input time from address WAIT input time from ASTB WAIT hold time from ASTB Delay from ASTB to WAIT WAIT input time from RD WAIT hold time from RD Delay from RD to WAIT Data input time from WAIT Delay from WAIT to RD Delay from WAIT to WR WAIT input time from WR WAIT hold time from WR Delay from WR to WAIT Symbol tDAWT tDSTWT tHSTWT tDSTWTH tDRWTL tHRWT tDRWTH tDWTID tDWTR tDWTW tDWWTL tHWWT tDWWTH VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V Conditions (2 + a)T - 40 1.5T - 40 (0.5 + n)T + 5 (1.5 + n)T - 40 T - 40 nT + 5 (1 + n)T - 40 0.5T - 5 0.5T 0.5T T - 40 nT + 5 (1 + n)T - 40 84 198 40 40 39 84 198 35 124 238 39 MIN. MAX. 198 79 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Remark T: a: n: tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.) 1 during address wait, otherwise, 0 number of wait states (n 0) 76 Data Sheet U11680EJ2V0DS00 PD784907, 784908 (3) Bus hold timing Parameter Delay from HLDRQ to float Delay from HLDRQ to HLDAK Delay from float to HLDAK Delay from HLDRQ to HLDAK Delay from HLDRQ to active Symbol tFQHC tDHQHHAH tDCFHA tDHQLHAL tDHAC VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V Conditions (2 + 4 + a + n)T + 50 (3 + 4 + a + n)T + 30 T + 30 2T + 40 T - 20 59 MIN. MAX. 765 825 109 199 Unit ns ns ns ns ns Remark T: a: n: tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.) 1 during address wait, otherwise, 0 number of wait states (n 0) (4) Refresh timing Parameter Random read/write cycle time REFRQ low-level pulse width Delay from ASTB to REFRQ Delay from RD to REFRQ Delay from WR to REFRQ Delay from REFRQ to ASTB REFRQ high-level pulse width Symbol tRC tWRFQL tDSTRFQ tDRRFQ tDWRFQ tDRFQST tWRFQH VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V Conditions 3T 1.5T - 25 0.5T - 9 1.5T - 9 1.5T - 9 0.5T - 9 1.5T - 25 MIN. 238 94 31 110 110 31 94 MAX. Unit ns ns ns ns ns ns ns Remark T: tCYK (system clock cycle time) VDD = 5.0 V T = 79 ns (MIN.) Data Sheet U11680EJ2V0DS00 77 PD784907, 784908 Serial Operation (TA = -40 to +85C, VDD = 3.5 to 5.5 V, AVSS = VSS = 0 V) (1) CSI, CSI3 Parameter Serial clock cycle time (SCK0, SCK3) Symbol tCYSK0 Input Conditions fCLK = fXX Except fCLK = fXX Output Except fCLK = fXX/8 fCLK = fXX/8 Serial clock low-level width (SCK0, SCK3) tWSKL0 Input fCLK = fXX Except fCLK = fXX Output Except fCLK = fXX/8 fCLK = fXX/8 Serial clock high-level width (SCK0, SCK3) tWSKH0 Input fCLK = fXX Except fCLK = fXX Output Except fCLK = fXX/8 fCLK = fXX/8 SI0, SI3 setup time (to SCK0, SCK3) SI0, SI3 hold time (from SCK0, SCK3) SO0, SO3 output delay time (from SCK0, SCK3) tHSSK0 External clock Internal clock tDSBSK1 CMOS push-pull output External clock Internal clock tDSBSK2 Open-drain output RL = 1 k When data is transferred External clock Internal clock 1/fCLK + 80 80 0 0 0 0 0.5tCYSK0 - 40 1/fCLK + 150 150 1/fCLK + 400 400 ns ns ns ns ns ns tSSSK0 MIN. 8/fXX 4/fCLK 8/fXX 16/fXX 4/fXX - 40 2/fCLK - 40 4/fXX - 40 8/fXX - 40 4/fXX - 40 2/fCLK - 40 4/fXX - 40 8/fXX - 40 80 ns ns MAX. Unit ns ns ns ns ns s s SO0, SO3 output hold time (from SCK0, SCK3) tHSBSK Remarks 1. The values in this table are those when fXX = 12.58 MHz, CL = 100 pF. 2. fCLK: system clock frequency (selectable from fXX, fXX/2, fXX/4, and fXX/8 by the standby control register (STBC)) 3. fXX: oscillation frequency (fXX = 12.58 MHz or fXX = 6.29 MHz) 78 Data Sheet U11680EJ2V0DS00 PD784907, 784908 (2) IOE1, IOE2 (TA = -40 to +85C, VDD = AVDD = 3.5 to 5.5 V, AVSS = VSS = 0 V) Parameter Serial clock cycle time (SCK1, SCK2) Symbol tCYSK1 Input Conditions VDD = 4.0 to 5.5 V MIN. 640 1,280 Output Internal, divided by 8 Serial clock low-level width (SCK1, SCK2) tWSKL1 Input VDD = 4.0 to 5.5 V T 280 600 Output Internal, divided by 8 Serial clock high-level width (SCK1, SCK2) tWSKH1 Input VDD = 4.0 to 5.5 V 0.5T - 40 280 600 Output Internal, divided by 8 SI1, SI2 setup time (to SCK1, SCK2) SI1, SI2 hold time (from SCK1, SCK2) SO1, SO2 output delay time (from SCK1, SCK2) SO1, SO2 output hold time (from SCK1, SCK2) tHSSK1 tDSOSK tHSOSK When data is transferred 40 0 0.5tCYSK1 - 40 50 ns ns ns tSSSK1 0.5T - 40 40 MAX. Unit ns ns ns ns ns ns ns ns ns ns Remarks 1. The values in this table are those when CL = 100 pF. 2. T: serial clock cycle set by software. The minimum value is 8/fXX. (3) UART, UART2 (TA = -40 to +85C, VDD = AVDD = 3.5 to 5.5 V, AVSS = VSS = 0 V) Parameter ASCK clock input cycle time Symbol tCYASK Conditions VDD = 4.5 to 5.5 V MIN. 160 320 ASCK clock low-level width tWASKL VDD = 4.5 to 5.5 V 65 120 ASCK clock high-level width tWASKH VDD = 4.5 to 5.5 V 65 120 MAX. Unit ns ns ns ns ns ns Data Sheet U11680EJ2V0DS00 79 PD784907, 784908 Clock Output Operation (TA = -40 to +85C, VDD = AVDD = 3.5 to 5.5 V, AVSS = VSS = 0 V) Parameter CLKOUT cycle time CLKOUT low-level width Symbol tCYCL tCLL nT VDD = 4.0 to 5.5 V, 0.5T - 10 0.5T - 20 CLKOUT high-levell width tCLH VDD = 4.0 to 5.5 V, 0.5T - 10 0.5T - 20 CLKOUT rising time tCLR VDD = 4.0 to 5.5 V VDD = 3.5 to 4.0 V CLKOUT falling time tCLF VDD = 4.0 to 5.5 V VDD = 3.5 to 4.0 V 0.3 0.3 Conditions MIN. 79 30 20 30 20 10 20 10 20 MAX. 32,000 Unit ns ns ns ns ns ns ns ns ns Remark n: T: Dividing ratio set by software in the CPU (n = 1, 2, 4, 8, and 16) tCYK (system clock cycle time) Other Operations (TA = -40 to +85C, VDD = AVDD = 3.5 to 5.5 V, AVSS = VSS = 0 V) Parameter NMI low-level width NMI high-level width INTP0 low-level width INTP0 high-level width INTP1 to INTP3 and CI low-level width INTP1 to INTP3 and CI high-level width INTP4 and INTP5 low-level width tWIT2L 10 10 10 10 Symbol tWNIL tWNIH tWIT0L tWIT0H tWIT1L tWIT1H Conditions MIN. 10 10 4tCYSMP 4tCYSMP 4tCYCPU 4tCYCPU MAX. Unit s s ns ns ns ns s s s s INTP4 and INTP5 high-level width tWIT2H RESET low-level widthNote RESET high-level width tWRSL tWRSH Note When the power is ON, secure the oscillation stabilization wait time with the RESET low-level width. Remark tCYSMP: sampling clock set by software tCYCPU: CPU operation clock set by software in the CPU 80 Data Sheet U11680EJ2V0DS00 PD784907, 784908 A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = AVREF1 = 3.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Resolution Total errorNote IEAD = 00H FR = 1 IEAD = 01H Quantization error Conversion time tCONV FR = 1 120/fCLK FR = 0 240/fCLK Sampling time tSAMP FR = 1 18/fCLK FR = 0 36/fCLK Analog input impedance AVREF1 impedance RAN RREF1 CS = 1 CS = 0, STOP mode 3 9.5 19.1 1.4 2.9 1,000 10 2.0 1.0 5.0 20 VDD = 4.5 to 5.5 V 1 Symbol Conditions MIN. 8 0.6 1.5 2.2 1/2 480 960 72 144 TYP. MAX. Unit bit % % % LSB s s s s M k mA AVDD power supply current AIDD1 AIDD2 A Note Quantization error is not included. This parameter is indicated as the ratio to the full-scale value. Caution To execute the conversion by the A/D converter set port 7, multiplexed with the A/D input lines, to output mode to prevent data from being inverted. Remark fCLK: system clock frequency (selectable from fXX, fXX/2, fXX/4, and fXX/8 by the standby control register (STBC)) IEBus Controller Characteristics (TA = -40 to +85C, VDD = AVDD = AVREF1 = 4.5 to 5.5 V, AVSS = VSS = 0 V) Parameter IEBus standard frequencyNote 1 Symbol fS Conditions Transfer speed: mode 1 CL = 50 pFNote 3 MIN. 6.20 TYP. 6.29 MAX. 6.39 1.5 0.7 0.85 Unit MHz Driver delay time (from tDTX TX output to bus line)Note 2 Receiver delay time (from tDRX bus line to RX input)Note 2 Transmission delay on busNote 2 tDBUS s s s Notes 1. The value conforms to the IEBus standard. The IEBus controller is operable within the range of the oscillator frequency of oscillator characteristics. 2. IEBus system clock: The value is measured when fX = 6.29 MHz. 3. C is the load capacitance of TX output line. Data Sheet U11680EJ2V0DS00 81 PD784907, 784908 Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode STOP mode VDDDR = 2.5 V, AVREF = 0 VNote 1 VDDDR = 3.5 to 5.5 V, AVREF = 0 VNote 1 VDD rising time VDD falling time VDD hold time (from STOP mode setting) STOP clear signal input time Oscillation settling time tWAIT Crystal resonator Ceramic resonator Input low voltage Input high voltage VIL VIH Specific pinsNote 2 30 5 0 0.9VDDDR 0.1VDDDR VDDDR ms ms V V tRVD tFVD tHVD tDREL 200 200 0 0 0.6 Conditions MIN. 2.5 2 10 TYP. MAX. 5.5 10 50 Unit V A A s s ms ms Notes 1. Valid when input voltages to the pins described in Note 2 satisfy VIL or VIH in the above table. 2. RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3, and P107/SO3 pins AC Timing Test Points VDD - 1 V 0.8 VDD or 2.2 V Test points 0.45 V 0.8 V 0.8 V 0.8 VDD or 2.2 V 82 Data Sheet U11680EJ2V0DS00 PD784907, 784908 Timing Waveform (1) Read operation tWSTH ASTB tSAST tHSTLA A8 to A19 tDSTID tDRST tDAID AD0 to AD7 tDSTR tDAR RD tWRL tFRA tDRID tHRA tHRID tDRA (2) Write operation tWSTH ASTB tSAST tHSTLA A8 to A19 tDSTOD tDWST tHWA AD0 to AD7 tDSTW tDAW WR tWWL tDWOD tSODWR tHWOD Data Sheet U11680EJ2V0DS00 83 PD784907, 784908 Hold Timing ASTB, A8 to A19, AD0 to AD7, RD, WR tFHQC HLDRQ tDHQHHAH HLDAK tDHQLHAL tDCFHA tDHAC External Wait Signal Input Timing (1) Read operation ASTB tDSTWTH tHSTWTH tDSTWT A8 to A19 AD0 to AD7 tDAWT RD tDRWTL WAIT tHRWT tDRWTH tDWTR tDWTID (2) Write operation ASTB tDSTWTH tHSTWTH tDSTWT A8 to A19 AD0 to AD7 tDAWT WR tDWWTL WAIT tHWWT tDWWTH tDWTW 84 Data Sheet U11680EJ2V0DS00 PD784907, 784908 Refresh Timing Waveform (1) Random read/write cycle tRC ASTB WR tRC RD tRC tRC tRC (2) When refresh memory is accessed for a read and write at the same time ASTB RD, WR tDSTRFQ tDRFQST tWRFQH REFRQ tWRFQL (3) Refresh after a read ASTB tDRFQST RD tDRRFQ REFRQ tWRFQL (4) Refresh after a write ASTB tDRFQST WR tDWRFQ REFRQ tWRFQL Data Sheet U11680EJ2V0DS00 85 PD784907, 784908 Serial Operation (CSI, CSI3) tWSKL0 SCK0, SCK3 tCYSK0 SI0, SI3 tDSBSK1 SO0, SO3 tHSBSK1 tSSSK0 tHSSK0 Input data tWSKH0 Output data Serial Operation (IOE1, IOE2) tWSKL1 SCK1, SCK2 tCYSK1 SI1, SI2 tDSOSK SO1, SO2 tHSOSK tSSSK1 tHSSK1 tWSKH1 Input data Output data Serial Operation (UART, UART2) tWASKH tWASKL ASCK, ASCK2 tCYASK Clock Output Timing tCLH tCLL CLKOUT tCLR tCYCL tCLF 86 Data Sheet U11680EJ2V0DS00 PD784907, 784908 Interrupt Request Input Timing tWNIH tWNIL NMI tWIT0H tWIT0L INTP0 tWIT1H tWIT1L CI, INTP1 to INTP3 tWIT2H tWIT2L INTP4, INTP5 Reset Input Timing tWRSH tWRSL RESET Data Sheet U11680EJ2V0DS00 87 PD784907, 784908 External Clock Timing tWXH tWXL X1 tXR tCYX tXF Data Retention Characteristics STOP mode setting VDD tHVD tFVD VDDDR tRVD tDREL tWAIT RESET NMI (Clearing by falling edge) NMI (Clearing by rising edge) 88 Data Sheet U11680EJ2V0DS00 PD784907, 784908 16. PACKAGE DRAWING 100 PIN PLASTIC QFP (14x20) A B 80 81 51 50 detail of lead end CD S Q R 100 1 31 30 F G H I M J P K M N L ITEM A B C D F G MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX. INCHES 0.9290.016 0.795 +0.009 -0.008 0.551 +0.009 -0.008 0.6930.016 0.031 0.024 0.012 +0.004 -0.005 0.006 0.026 (T.P.) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 +0.005 -0.004 0.0040.004 55 0.119 MAX. P100GF-65-3BA1-3 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. Remark The shape and material of the ES version are the same as those of the corresponding mass-produced product. H I J K L M N P Q R S Data Sheet U11680EJ2V0DS00 89 PD784907, 784908 17. RECOMMENDED SOLDERING CONDITIONS The PD784908 should be soldered under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 17-1. Soldering Conditions for Surface Mount Type PD784907GF-xxx-3BA: 100-pin plastic QFP (14 x 20 mm) PD784908GF-xxx-3BA: 100-pin plastic QFP (14 x 20 mm) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C Time: 30 seconds max. (210C or higher) Count: three times or less Package peak temperature: 215C Time: 40 seconds or max. (200C or higher) Count: three times or less Wave soldering Solder bath temperature: 260C max. Time: 10 seconds max. Count : 1 Preheating temperature: 120C max. (package surface temperature) Pin temperature: 300C Time: 3 seconds max. (per pin row) WS60-00-1 Recommended Condition Symbol IR35-00-3 VPS VP15-00-3 Partial heating method -- Caution Do not use different soldering methods together (except for partial heating). 90 Data Sheet U11680EJ2V0DS00 PD784907, 784908 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for system development using the PD784908. Also refer to (5) Cautions on using development tools. (1) Language processing software RA78K4 CC78K4 DF784908 CC78K4-L Assembler package common to 78K/IV Series C compiler package common to 78K/IV Series Device file for PD784908 Subseries C compiler library source file common to 78K/IV Series (2) PROM write tools PG-1500 PA-78P4908GF PG-1500 controller PROM programmer Programmer adapter, connects to PG-1500 Control program for PG-1500 (3) Debugging tools * When using the in-circuit emulator IE-78K4-NS IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF IE-784908-NS-EM1 NP-100GFNote EV-9200GF-100 ID78K4-NS SM78K4 DF784908 In-circuit emulator common to 78K/IV Series Power supply unit for IE-78K4-NS Interface adapter when a PC-9800 Series computer (except notebook type) is used as the host machine (C bus supported) PC card and interface cable when a notebook type is used as the host machine (PCMCIA socket supported) Interface adapter when an IBM PC/ATTM or compatible is used as the host machine (ISA bus supported) Adapter when a PC that incorporates a PCI bus is used as the host machine Emulation board to emulate PD784908 Subseries Emulation probe for 100-pin plastic QFP (GF-3BA type) Socket to be mounted on target system board made for 100-pin plastic QFP (GF-3BA type). Used in LCC mode. Integrated debugger for IE-78K4-NS System simulator common to 78K/IV Series Device file for PD784908 Subseries Note Under development Data Sheet U11680EJ2V0DS00 91 PD784907, 784908 * When using the in-circuit emulator IE-784000-R IE-784000-R IE-70000-98-IF-C IE-70000-PC-IF-C IE-70000-PCI-IF IE-78000-R-SV3 IE-784908-NS-EM1 IE-784908-R-EM1 IE-784000-R-EM IE-78K4-R-EX2 In-circuit emulator common to 78K/IV Series Interface adapter when a PC-9800 Series computer (except notebook type) is used as the host machine (C bus supported) Interface adapter when an IBM PC/AT or compatible is used as the host machine (ISA bus supported) Adapter when a PC that incorporates a PCI bus is used as the host machine Interface adapter and cable when the EWS is used as the host machine Emulation board to emulate PD784908 Subseries Emulation board common to 78K/IV Series Conversion board for emulation probes required to use the IE-784908-NSEM1 on the IE-784000-R. The board is not needed when the conventional product IE-784908-R-EM1 is used. EP-78064-GF-R EV-9200GF-100 ID78K4 SM78K4 DF784908 Emulation probe for 100-pin plastic QFP (GF-3BA type) Socket to be mounted on target system board made for 100-pin plastic QFP (GF-3BA type) Integrated debugger for IE-784000-R System simulator common to 78K/IV Series Device file for PD784908 Subseries (4) Real-time OS RX78K/IV MX78K4 Real-time OS for 78K/IV Series OS for 78K/IV Series 92 Data Sheet U11680EJ2V0DS00 PD784907, 784908 (5) Cautions on using development tools * The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784908. * The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784908. * The NP-100GF is a product made by Naito Densei Machidaseisakusho Co., Ltd. (+81-44-822-3813). Contact an NEC distributor regarding the purchase of these products. * The host machines and OSs suitable for each software are as follows. Host Machine [OS] PC PC-9800 Series [WindowsTM] IBM PC/AT and compatibles [Japanese/English Windows] Note Note Note Note Note EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] NEWSTM (RISC) [NEWS-OSTM] -- -- -- Software RA78K4 CC78K4 PG-1500 controller ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4 Note DOS-based software Data Sheet U11680EJ2V0DS00 93 PD784907, 784908 APPENDIX B RELATED DOCUMENTS Documents related to devices Document Name Document No. Japanese English This manual U11681E U11787E -- U10905E -- -- U10095E PD784907, 784908 Data Sheet PD78P4908 Data Sheet PD784908 Subseries User's Manual Hardware PD784908 Subseries Special Function Register Table 78K/IV Series User's Manual Instructions 78K/IV Series Instruction Table 78K/IV Series Instruction Set 78K/IV Series Application Note Software Basics U11680J U11681J U11787J U11589J U10905J U10594J U10595J U10095J Documents related to development tools (User's Manual) Document Name Document No. Japanese RA78K4 Assembler Package Language Operation RA78K4 Structured Assembler Preprocessor CC78K4 C Compiler Language Operation PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOSTM) Based PG-1500 Controller IBM PC Series (PC DOSTM) Based IE-78K4-NS IE-784000-R IE-784908-R-EM1 IE-784908-NS-EM1 EP-78064 SM78K4 System Simulator Windows Based SM78K Series System Simulator ID78K4-NS Integrated Debugger PC Based ID78K4 Integrated Debugger Windows Based ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Based Reference External Part User Open Interface Specifications Reference Reference Reference U11162J U11334J U11743J U11571J U11572J U11940J EEU-704 EEU-5008 U13356J U12903J U11876J U13743J EEU-934 U10093J U10092J U12796J U10440J U11960J English U11162E U11334E U11743E U11571E U11572E U11940E EEU-1291 U10540E U13356E U12903E -- Under preparation EEU-1469 U10093E U10092E U12796E U10440E U11960E Caution The above documents may be revised without notice. Use the latest versions when you design application systems. 94 Data Sheet U11680EJ2V0DS00 PD784907, 784908 Documents related to embedded software (User's Manual) Document Name Document No. Japanese 78K/IV Series Real-Time OS Fundamental Installation Debugger 78K/IV Series OS MX78K4 Fundamental U10603J U10604J U10364J U11779J English U10603E U10604E -- -- Other documents Document Name Document No. Japanese NEC IC PACKAGE MANUAL (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Device NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Quality Assurance for Semiconductor Devices Guide to Microcontroller-Related Products by Third Parties -- C10535J C11531J C10983J C11892J -- U11416J English C13388E C10535E C11531E C10983E C11892E MEI-1202 -- Caution The above documents may be revised without notice. Use the latest versions when you design application systems. Data Sheet U11680EJ2V0DS00 95 PD784907, 784908 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 96 Data Sheet U11680EJ2V0DS00 PD784907, 784908 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J98. 11 Data Sheet U11680EJ2V0DS00 97 PD784907, 784908 FIP, IEBus, and EEPROM are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents in this publication may include preliminary version. However, what preliminary versions are not marked as such. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5 Data Sheet U11680EJ2V0DS00 |
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